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TP13064BDW PDF预览

TP13064BDW

更新时间： 2024-01-06 12:39:26
品牌 Logo 应用领域
德州仪器 - TI 解码器过滤器编解码器电信集成电路电信电路光电二极管LTEPC
页数 文件大小 规格书
21页 301K
描述
MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER

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TP13064BDW 技术参数

是否Rohs认证：符合生命周期：Obsolete
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.71
Is Samacsys：N其他特性：FULL DUPLEX
压伸定律：MU-LAW滤波器：YES
最大增益公差：0.15 dBJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：12.8 mm
线性编码：NOT AVAILABLE湿度敏感等级：1
负电源额定电压：-5 V功能数量：1
端子数量：20工作模式：SYNCHRONOUS/ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：+-5 V认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Codecs
最大压摆率：11 mA标称供电电压：5 V
表面贴装：YES技术：CMOS
电信集成电路类型：PCM CODEC温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.5 mm
Base Number Matches：1

TP13064BDW 数据手册

 浏览型号TP13064BDW的Datasheet PDF文件第2页浏览型号TP13064BDW的Datasheet PDF文件第3页浏览型号TP13064BDW的Datasheet PDF文件第4页浏览型号TP13064BDW的Datasheet PDF文件第5页浏览型号TP13064BDW的Datasheet PDF文件第6页浏览型号TP13064BDW的Datasheet PDF文件第7页 
TP3064B, TP3067B, TP13064B, TP13067B  
MONOLITHIC SERIAL INTERFACE  
COMBINED PCM CODEC AND FILTER  
SCTS031D – MAY 1990 –REVISED JULY 1996  
Complete PCM Codec and Filtering  
Systems Include:  
– Transmit High-Pass and Low-Pass  
Filtering  
µ-Law – TP13064B and TP3064B  
A-Law – TP13067B and TP3067B  
±5-V Operation  
Low Operating Power . . . 70 mW Typ  
Power-Down Standby Mode . . . 3 mW Typ  
Automatic Power Down  
– Receive Low-Pass Filter With (sin x)/x  
Correction  
– Active RC Noise Filters  
– µ-Law or A-Law Compatible Coder and  
Decoder  
TTL- or CMOS-Compatible Digital Interface  
Maximizes Line Interface Card Circuit  
Density  
– Internal Precision Voltage Reference  
– Serial I/O Interface  
Improved Versions of National  
Semiconductor TP3064, TP3067, TP3064-X,  
and TP3067-X  
– Internal Autozero Circuitry  
description  
DW OR N PACKAGE  
(TOP VIEW)  
The TP3064B, TP3067B, TP13064B, and  
TP13067B each comprise a single-chip pulse-  
code-modulation encoder and decoder (PCM  
codec), and PCM line filter. They also provide  
band-pass filtering of the analog signals prior to  
the encoding, and low-pass filtering after the  
decodingofvoicesignalsandcall-progresstones.  
All the functions required to interface a full-duplex  
(2-wire) voice telephone circuit with a time-divi-  
sion-multiplexed (TDM) system are included  
on-chip. These devices are pin-for-pin compatible  
with the National Semiconductor TP3064 and  
TP3067. Primary applications include:  
VPO+  
ANLG GND  
VPO–  
V
BB  
VFXI+  
VFXI–  
GSX  
ANLG LOOP  
TSX  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
VPI  
VFRO  
V
CC  
FSR  
DR  
14 FSX  
13 DX  
12 BCLKX  
11 MCLKX  
BCLKR/CLKSEL  
MCLKR/PDN 10  
•
Line interface for digital transmission and  
switching of T1 carrier, PABX (private  
automated branch exchange), and central  
office telephone systems  
•
•
•
•
Subscriber line concentrators  
Digital-encryption systems  
Digital voice-band data-storage systems  
Digital signal processing  
These devices are designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A  
conversion) as well as the transmit and receive filtering functions in a PCM system, and are intended to be used  
at the analog termination of a PCM line or trunk. They require a transmit master clock and a receive master clock  
that may be asynchronous (1.536 MHz, 1.544 MHz, or 2.048 MHz), transmit and receive data clocks that are  
synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive  
frame-sync pulses. The TP3064B and TP13064B contain patented circuitry to achieve low transmit channel  
idle noise and are not recommended for applications in which the composite signals on the transmit side are  
below –55 dBm0.  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the CMOS gates.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...21

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与TP13064BDW相关器件

型号 品牌 获取价格 描述 数据表
TP13064BFN TI

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 		MU-LAW, PCM CODEC, PQCC20
TP13064BFNR TI

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 		MU-LAW, PCM CODEC, PQCC20
TP13064BJ TI

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 		MU-LAW, PCM CODEC, CDIP20
TP13064BN TI

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 		MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
TP13067A TI

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 		MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
TP13067ADW TI

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 		MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
TP13067ADWR TI

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 		暂无描述
TP13067AJ ETC

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 		A-Law CODEC
TP13067AN TI

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 		MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
TP13067B TI

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 		MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER

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