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TNETV6421INZDU4

更新时间： 2024-11-27 11:08:03
品牌 Logo 应用领域
德州仪器 - TI 时钟动态存储器双倍数据速率控制器微控制器微控制器和处理器外围集成电路数字信号处理器
页数 文件大小 规格书
59页 563K
描述
C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2、SDRAM | ZDU | 376 | 0 to 90

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TNETV6421INZDU4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：HBGA,针数：376
Reach Compliance Code：compliant风险等级：5.63
地址总线宽度：22桶式移位器：NO
边界扫描：YES最大时钟频率：30 MHz
外部数据总线宽度：8格式：FIXED POINT
内部总线架构：MULTIPLEJESD-30 代码：S-PBGA-B376
JESD-609代码：e1长度：23 mm
低功率模式：YES湿度敏感等级：3
端子数量：376最高工作温度：90 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：HBGA封装形状：SQUARE
封装形式：GRID ARRAY, HEAT SINK/SLUG峰值回流温度（摄氏度）：260
座面最大高度：2.48 mm最大供电电压：1.26 V
最小供电电压：1.14 V标称供电电压：1.2 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：23 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

TNETV6421INZDU4 数据手册

 浏览型号TNETV6421INZDU4的Datasheet PDF文件第2页浏览型号TNETV6421INZDU4的Datasheet PDF文件第3页浏览型号TNETV6421INZDU4的Datasheet PDF文件第4页浏览型号TNETV6421INZDU4的Datasheet PDF文件第5页浏览型号TNETV6421INZDU4的Datasheet PDF文件第6页浏览型号TNETV6421INZDU4的Datasheet PDF文件第7页 
TMS320C6421  
Fixed-Point Digital Signal Processor  
www.ti.com  
SPRS346A–JANUARY 2007–REVISED MARCH 2007  
1 TMS320C6421 Fixed-Point Digital Signal Processor  
1.1 Features  
[Flexible Allocation]  
512K-Bit (64K-Byte) L2 Unified Mapped  
RAM/Cache [Flexible Allocation]  
•
High-Performance Digital Signal Processor  
(C6421)  
–
–
–
–
–
–
–
2.5-, 2.-, 1.67-ns Instruction Cycle Time  
400-, 500-, 600-MHz C64x+™ Clock Rate  
Eight 32-Bit C64x+ Instructions/Cycle  
3200, 4000, 4800 MIPS  
Fully Software-Compatible With C64x  
Commercial and Extended Temperature  
Ranges  
•
•
Endianess: Supports Both Little Endian and  
Big Endian  
External Memory Interfaces (EMIFs)  
–
16-Bit DDR2 SDRAM Memory Controller  
With 128M-Byte Address Space (1.8-V I/O)  
Asynchronous 8-Bit-Wide EMIF (EMIFA)  
With up to 64M-Byte Address Reach  
–
•
VelociTI.2™ Extensions to VelociTI™  
Advanced Very-Long-Instruction-Word (VLIW)  
TMS320C64x+™ DSP Core  
•
Flash Memory Interfaces  
•
•
NOR (8-Bit-Wide Data)  
NAND (8-Bit-Wide Data)  
–
Eight Highly Independent Functional Units  
With VelociTI.2 Extensions:  
•
•
Enhanced Direct-Memory-Access (EDMA)  
Controller (64 Independent Channels)  
•
Six ALUs (32-/40-Bit), Each Supports  
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit  
Arithmetic per Clock Cycle  
Two 64-Bit General-Purpose Timers (Each  
Configurable as Two 32-Bit Timers)  
•
Two Multipliers Support Four 16 x 16-Bit  
Multiplies (32-Bit Results) per Clock  
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit  
Results) per Clock Cycle  
•
•
•
One 64-Bit Watch Dog Timer  
One UART With RTS and CTS Flow Control  
Master/Slave Inter-Integrated Circuit  
(I2C Bus™)  
–
Load-Store Architecture With Non-Aligned  
Support  
•
Multichannel Buffered Serial Port (McBSP0)  
–
–
–
–
64 32-Bit General-Purpose Registers  
Instruction Packing Reduces Code Size  
All Instructions Conditional  
–
–
–
–
–
–
I2S and TDM  
AC97 Audio Codec Interface  
SPI  
Standard Voice Codec Interface (AIC12)  
Telecom Interfaces – ST-Bus, H-100  
128 Channel Mode  
Additional C64x+™ Enhancements  
•
•
Protected Mode Operation  
Exceptions Support for Error Detection  
and Program Redirection  
•
Multichannel Audio Serial Port (McASP0)  
Four Serializers and SPDIF (DIT) Mode  
•
Hardware Support for Modulo Loop  
Auto-Focus Module Operation  
–
•
•
16-Bit Host-Port Interface (HPI)  
•
C64x+ Instruction Set Features  
10/100 Mb/s Ethernet MAC (EMAC)  
–
–
–
–
–
–
Byte-Addressable (8-/16-/32-/64-Bit Data)  
8-Bit Overflow Protection  
Bit-Field Extract, Set, Clear  
Normalization, Saturation, Bit-Counting  
VelociTI.2 Increased Orthogonality  
C64x+ Extensions  
–
–
IEEE 802.3 Compliant  
Supports Multiple Media Independent  
Interfaces (MII, RMII)  
–
Management Data I/O (MDIO) Module  
•
•
•
•
•
•
VLYNQ™ Interface (FPGA Interface)  
Three Pulse Width Modulator (PWM) Outputs  
On-Chip ROM Bootloader  
•
•
Compact 16-bit Instructions  
Additional Instructions to Support  
Complex Multiplies  
Individual Power-Savings Modes  
Flexible PLL Clock Generators  
•
C64x+ L1/L2 Memory Architecture  
–
128K-Bit (16K-Byte) L1P Program  
RAM/Cache [Flexible Allocation]  
IEEE-1149.1 (JTAG™)  
Boundary-Scan-Compatible  
–
128K-Bit (16K-Byte) L1D Data RAM/Cache  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this document.  
All trademarks are the property of their respective owners.  
PRODUCT PREVIEW information concerns products in the  
formative or design phase of development. Characteristic data and  
other specifications are design goals. Texas Instruments reserves  
the right to change or discontinue these products without notice.  
Copyright © 2007–2007, Texas Instruments Incorporated  
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