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TN80L186EB13 PDF预览

TN80L186EB13

更新时间: 2024-11-25 21:54:27
品牌 Logo 应用领域
英特尔 - INTEL 微控制器和处理器外围集成电路微处理器装置动态存储器时钟
页数 文件大小 规格书
59页 779K
描述
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

TN80L186EB13 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:LCC包装说明:QCCJ, LDCC84,1.2SQ
针数:84Reach Compliance Code:unknown
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.62其他特性:DRAM REFRESH CONTROLLER; 3 PROGRAMMABLE TIMERS; EMULATION HARDWARE
地址总线宽度:20位大小:16
边界扫描:NO最大时钟频率:26 MHz
外部数据总线宽度:16格式:FIXED POINT
集成缓存:NOJESD-30 代码:S-PQCC-J84
JESD-609代码:e0长度:29.3116 mm
低功率模式:YESDMA 通道数量:
外部中断装置数量:6串行 I/O 数:2
端子数量:84片上数据RAM宽度:
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC84,1.2SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/5 V认证状态:Not Qualified
RAM(字数):0座面最大高度:4.83 mm
速度:13 MHz子类别:Microprocessors
最大压摆率:73 mA最大供电电压:5.5 V
最小供电电压:2.7 V标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:29.3116 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR
Base Number Matches:1

TN80L186EB13 数据手册

 浏览型号TN80L186EB13的Datasheet PDF文件第2页浏览型号TN80L186EB13的Datasheet PDF文件第3页浏览型号TN80L186EB13的Datasheet PDF文件第4页浏览型号TN80L186EB13的Datasheet PDF文件第5页浏览型号TN80L186EB13的Datasheet PDF文件第6页浏览型号TN80L186EB13的Datasheet PDF文件第7页 
80C186EB/80C188EB AND 80L186EB/80L188EB  
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS  
X
True CMOS Inputs and Outputs  
Full Static Operation  
X
Y
Y
Integrated Feature Set  
Available in Extended Temperature  
b a  
Ð Low-Power Static CPU Core  
Ð Two Independent UARTs each with  
an Integral Baud Rate Generator  
Ð Two 8-Bit Multiplexed I/O Ports  
Ð Programmable Interrupt Controller  
Ð Three Programmable 16-Bit  
Timer/Counters  
Range ( 40 C to 85 C)  
§
§
Speed Versions Available (3V):  
Y
Y
Ð 16 MHz (80L186EB16/80L188EB16)  
Ð 13 MHz (80L186EB13/80L188EB13)  
Ð 8 MHz (80L186EB8/80L188EB8)  
Low-Power Operating Modes:  
Ð Idle Mode Freezes CPU Clocks but  
keeps Peripherals Active  
Ð Powerdown Mode Freezes All  
Internal Clocks  
Ð Clock Generator  
Ð Ten Programmable Chip Selects with  
Integral Wait-State Generator  
Ð Memory Refresh Control Unit  
Ð System Level Testing Support (ONCE  
Mode)  
Y
Y
Supports 80C187 Numeric Coprocessor  
Interface (80C186EB PLCC Only)  
Y
Y
Direct Addressing Capability to 1 Mbyte  
Memory and 64 Kbyte I/O  
Available In:  
Ð 80-Pin Quad Flat Pack (QFP)  
Ð 84-Pin Plastic Leaded Chip Carrier  
(PLCC)  
Speed Versions Available (5V):  
Ð 25 MHz (80C186EB25/80C188EB25)  
Ð 20 MHz (80C186EB20/80C188EB20)  
Ð 13 MHz (80C186EB13/80C188EB13)  
Ð 80-Pin Shrink Quad Flat Pack (SQFP)  
The 80C186EB is a second generation CHMOS High-Integration microprocessor. It has features that are new  
to the 80C186 family and include a STATIC CPU core, an enhanced Chip Select decode unit, two independent  
Serial Channels, I/O ports, and the capability of Idle or Powerdown low power modes.  
272433–1  
*Other brands and names are the property of their respective owners.  
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or  
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make  
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.  
October 1995  
COPYRIGHT INTEL CORPORATION, 1995  
Order Number: 272433-004  
©
1

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