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TN1219

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LatticeECP3 and Marvell 10 Gbps Physical/MAC Layer Interoperability

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LatticeECP3 and Marvell 10 Gbps  
Physical/MAC Layer Interoperability  
July 2010  
Technical Note TN1219  
Introduction  
This technical note describes a Physical/MAC Layer 10-Gigabit Ethernet interoperability test between a  
LatticeECP3™ device and the Marvell Alaska 88X2040 device. The test exercises the Physical/MAC Layer (up to  
the MAC client interface) of the 10-Gigabit Ethernet protocol stack on the LatticeECP3 device.  
Specifically, the document discusses the following topics:  
• Overview of LatticeECP3™ devices and Marvell Alaska 88X2040 devices  
• Physical/MAC layer interoperability setup, testing, and results  
XAUI Interoperability  
XAUI is a high-speed interconnect that offers reduced pin count and the ability to drive up to 20” of PCB trace on  
standard FR-4 material. In order to connect a 10-Gigabit Ethernet MAC to an off-chip PHY device, an XGMII inter-  
face is used. The XGMII is a low-speed parallel interface for short range (approximately 2”) interconnects.  
XAUI interoperability is based on the 10-Gigabit Ethernet standard (IEEE Standard 802.3ae-2002). Two XAUI link  
partners can be directly plugged into a XAUI backplane. Both boards are capable of generating and checking pack-  
ets.  
The board that sources packets is capable of keeping a detailed count of the number of packets transmitted while  
the sink board is capable of keeping detailed statistics on the number of packets received and errors associated  
with the packets. The XAUI backplane is also called the XAUI test channel. A typical test setup is shown in  
Figure 1.  
Each reference station must be a line card that is directly plugged into the XAUI test channel. Both DUTs are  
required to have their own clock domain. Synchronous clocking (distributing a single clock to the two DUTs) is not  
allowed. Local management indicators on the DUT (reference stations) that provide information on link level errors,  
such as CRC errors, are also needed. A DUT is called a Type #1 device if it is capable of transmitting and checking  
packets.  
A DUT is called a Type #2a device if it receives packets and does a RX to TX loopback through the XGMII and  
sends the packets back to the transmitting station, which is a Type #1 device. The Type #1 device then checks the  
received packets for errors. Figure 1 shows a setup where one DUT is of Type #1 and the other is of Type #2a.  
The LatticeECP3 and Marvell Alaska 88X2040 interoperability exercises the LatticeECP3 Physical and MAC lay-  
ers.  
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand  
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.  
www.latticesemi.com  
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