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TMSDVC5402PGE100G4 PDF预览

TMSDVC5402PGE100G4

更新时间： 2024-11-25 11:06:35
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德州仪器 - TI 控制器微控制器微控制器和处理器数字信号处理器
页数 文件大小 规格书
68页 939K
描述
数字信号处理器 | PGE | 144 | 0 to 0

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TMSDVC5402PGE100G4 数据手册

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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000  
D
D
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Advanced Multibus Architecture With Three  
Separate 16-Bit Data Memory Buses and  
One Program Memory Bus  
D
D
D
D
Arithmetic Instructions With Parallel Store  
and Parallel Load  
Conditional Store Instructions  
Fast Return From Interrupt  
40-Bit Arithmetic Logic Unit (ALU),  
Including a 40-Bit Barrel Shifter and Two  
Independent 40-Bit Accumulators  
On-Chip Peripherals  
– Software-Programmable Wait-State  
Generator and Programmable Bank  
Switching  
– On-Chip Phase-Locked Loop (PLL) Clock  
Generator With Internal Oscillator or  
External Clock Source  
– Two Multichannel Buffered Serial Ports  
(McBSPs)  
– Enhanced 8-Bit Parallel Host-Port  
Interface (HPI8)  
17- × 17-Bit Parallel Multiplier Coupled to a  
40-Bit Dedicated Adder for Non-Pipelined  
Single-Cycle Multiply/Accumulate (MAC)  
Operation  
D
D
D
Compare, Select, and Store Unit (CSSU) for  
the Add/Compare Selection of the Viterbi  
Operator  
Exponent Encoder to Compute an  
Exponent Value of a 40-Bit Accumulator  
Value in a Single Cycle  
– Two 16-Bit Timers  
– Six-Channel Direct Memory Access  
(DMA) Controller  
Two Address Generators With Eight  
Auxiliary Registers and Two Auxiliary  
Register Arithmetic Units (ARAUs)  
D
Power Consumption Control With IDLE1,  
IDLE2, and IDLE3 Instructions With  
Power-Down Modes  
D
D
Data Bus With a Bus-Holder Feature  
Extended Addressing Mode for 1M × 16-Bit  
Maximum Addressable External Program  
Space  
D
D
CLKOUT Off Control to Disable CLKOUT  
On-Chip Scan-Based Emulation Logic,  
†
IEEE Std 1149.1 (JTAG) Boundary Scan  
D
D
D
D
D
D
4K x 16-Bit On-Chip ROM  
Logic  
16K x 16-Bit Dual-Access On-Chip RAM  
D
D
10-ns Single-Cycle Fixed-Point Instruction  
Execution Time (100 MIPS) for 3.3-V Power  
Supply (1.8-V Core)  
Single-Instruction-Repeat and  
Block-Repeat Operations for Program Code  
Block-Memory-Move Instructions for  
Efficient Program and Data Management  
Available in a 144-Pin Plastic Low-Profile  
Quad Flatpack (LQFP) (PGE Suffix) and a  
144-Pin Ball Grid Array (BGA) (GGU Suffix)  
Instructions With a 32-Bit Long Word  
Operand  
Instructions With Two- or Three-Operand  
Reads  
NOTE:This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview  
(literature number SPRU307).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 2000, Texas Instruments Incorporated  
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1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...68

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