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TMS470R1A256PZ-TR

更新时间： 2024-09-24 13:14:51
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德州仪器 - TI 闪存微控制器
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TMS470R1A256  
16/32-Bit RISC Flash Microcontroller  
www.ti.com  
SPNS100–NOVEMBER 2004  
•
•
High-Performance Static CMOS Technology  
– Standard CAN Controller (SCC)  
TMS470R1x 16/32-Bit RISC Core  
(ARM7TDMI™)  
• 16-Mailbox Capacity  
• Fully Compliant With CAN Protocol,  
– 24-MHz System Clock (48-MHz Pipeline  
Mode)  
Version 2.0B  
– Class II Serial Interface (C2SIb)  
– Independent 16/32-Bit Instruction Set  
– Open Architecture With Third-Party Support  
– Built-In Debug Module  
• Two Selectable Data Rates  
• Normal Mode 10.4 Kbps and 4X Mode 41.6  
Kbps  
– Big-Endian Format Utilized  
•
High-End Timer (HET)  
•
Integrated Memory  
– 16 Programmable I/O Channels:  
• 14 High-Resolution Pins  
• 2 Standard-Resolution Pins  
– High-Resolution Share Feature (XOR)  
– High-End Timer RAM  
– 256K-Byte Program Flash  
• One Bank With 14 Contiguous Sectors  
• Internal State Machine for Programming  
and Erase  
– 12K-Byte Static RAM (SRAM)  
Operating Features  
• 64-Instruction Capacity  
•
•
•
10-Bit Multi-Buffered ADC (MibADC)  
16-Channel  
– Core Supply Voltage (VCC): 1.81 V–2.05 V  
– I/O Supply Voltage (VCCIO): 3.0 V–3.6 V  
– Low-Power Modes: STANDBY and HALT  
– Industrial Temperature Ranges  
470+ System Module  
– 64-Word FIFO Buffer  
– Single- or Continuous-Conversion Modes  
– 1.55 µs Minimum Sample and Conversion  
Time  
– Calibration Mode and Self-Test Features  
Eight External Interrupts  
– 32-Bit Address Space Decoding  
•
•
•
– Bus Supervision for Memory and  
Peripherals  
Flexible Interrupt Handling  
– Analog Watchdog (AWD) Timer  
– Real-Time Interrupt (RTI)  
11 Dedicated GIO Pins, 1 Input-Only GIO Pin,  
and 38 Additional Peripheral I/Os (A256)  
•
External Clock Prescale (ECP) Module  
– System Integrity and Failure Detection  
– Programmable Low-Frequency External  
Clock (CLK)  
•
•
Zero-Pin Phase-Locked Loop (ZPLL)-Based  
Clock Module With Prescaler  
•
•
Compatible ROM Device  
– Multiply-by-4 or -8 Internal ZPLL Option  
– ZPLL Bypass Mode  
On-Chip Scan-Base Emulation Logic, IEEE  
Standard 1149.1 (JTAG) Test-Access Port  
(1)  
Six Communication Interfaces:  
– Two Serial Peripheral Interfaces (SPIs)  
• 255 Programmable Baud Rates  
•
100-Pin Plastic Low-Profile Quad Flatpack (PZ  
Suffix)  
– Two Serial Communications Interfaces  
(SCIs)  
(1) The test-access port is compatible with the IEEE Standard  
1149.1-1990, IEEE Standard Test-Access Port and Boundary  
Scan Architecture. Boundary scan is not supported on this  
device.  
• 224 Selectable Baud Rates  
• Asynchronous/Isosynchronous Modes  
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004, Texas Instruments Incorporated  
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