TMS470R1A128
16/32-Bit RISC Flash Microcontroller
www.ti.com
SPNS098B–JULY 2005–REVISED AUGUST 2006
FEATURES
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Six Communication Interfaces:
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High-Performance Static CMOS Technology
– Two Serial Peripheral Interfaces (SPIs)
• 255 Programmable Baud Rates
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TMS470R1x 16/32-Bit RISC Core
(ARM7TDMI™)
– Two Serial Communications Interfaces
(SCIs)
– 28-MHz System Clock (48-MHz Pipeline
Mode)
• 224 Selectable Baud Rates
• Asynchronous/Isosynchronous Modes
– Standard CAN Controller (SCC)
• 16-Mailbox Capacity
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
– Big-Endian Format Utilized
• Fully Compliant with CAN Protocol,
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Integrated Memory
Version 2.0B
– 128K-Byte Program Flash
– Class II Serial Interface (C2SIa)
• One Bank With Ten Contiguous Sectors
• Two Selectable Data Rates
• Internal State Machine for Programming
• Normal Mode 10.4 Kbps and 4X Mode
and Erase
41.6 Kbps
– 8K-Byte Static RAM (SRAM)
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High-End Timer (HET)
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Operating Features
– 16 Programmable I/O Channels:
• 14 High-Resolution Pins
– Core Supply Voltage (VCC): 1.81 V–2.05 V
– I/O Supply Voltage (VCCIO): 3.0 V–3.6 V
– Low-Power Modes: STANDBY and HALT
– Extended Industrial Temperature Ranges
470+ System Module
• 2 Standard-Resolution Pins
– High-Resolution Share Feature (XOR)
– HET RAM (64-Instruction Capacity)
10-Bit Multi-Buffered ADC (MibADC)
16-Channel
– 32-Bit Address Space Decoding
– 64-Word FIFO Buffer
– Bus Supervision for Memory and
Peripherals
– Single- or Continuous-Conversion Modes
– Analog Watchdog (AWD) Timer
– Real-Time Interrupt (RTI)
– 1.55 µs Minimum Sample and Conversion
Time
– Calibration Mode and Self-Test Features
8 External Interrupts
– System Integrity and Failure Detection
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Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
Flexible Interrupt Handling
– Multiply-by-4 or -8 Internal ZPLL Option
– ZPLL Bypass Mode
11 Dedicated GIO Pins, 1 Input-Only GIO Pin,
and 38 Additional Peripheral I/Os
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External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
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On-Chip Scan-Base Emulation Logic, IEEE
Standard 1149.1 (1) (JTAG) Boundary-Scan
Logic
100-Pin Plastic Low-Profile Quad Flatpack
(PZ Suffix)
(1) The test-access port is compatible with the IEEE Standard
1149.1-1990, IEEE Standard Test-Access Port and Boundary
Scan Architecture. Boundary scan is not supported on this
device.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ARM7TDMI is a trademark of Advanced RISC Machines (ARM) Limited.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated