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TMS470R1A128 PDF预览

TMS470R1A128

更新时间: 2024-11-11 22:22:47
品牌 Logo 应用领域
德州仪器 - TI 闪存微控制器
页数 文件大小 规格书
45页 436K
描述
16/32-Bit RISC Flash Microcontrollers

TMS470R1A128 数据手册

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TMS470R1A128  
16/32-Bit RISC Flash Microcontrollers  
www.ti.com  
SPNS098JANUARY 2005  
FEATURES  
Asynchronous/Isosynchronous Modes  
– Standard CAN Controller (SCC)  
16-Mailbox Capacity  
High-Performance Static CMOS Technology  
TMS470R1x 16/32-Bit RISC Core  
(ARM7TDMI™)  
Fully Compliant with CAN Protocol,  
– 28-MHz System Clock (48-MHz Pipeline  
Mode)  
Version 2.0B  
– Class II Serial Interface (C2SIa)  
– Independent 16/32-Bit Instruction Set  
– Open Architecture With Third-Party Support  
– Built-In Debug Module  
Two Selectable Data Rates  
Normal Mode 10.4 Kbps and 4X Mode 41.6  
Kbps  
– Big-Endian Format Utilized  
High-End Timer (HET)  
Integrated Memory  
– 16 Programmable I/O Channels:  
14 High-Resolution Pins  
– 128K-Byte Program Flash  
One Bank With Ten Contiguous Sectors  
2 Standard-Resolution Pins  
– High-Resolution Share Feature (XOR)  
– HET RAM (64-Instruction Capacity)  
Internal State Machine for Programming  
and Erase  
– 8K-Byte Static RAM (SRAM)  
Operating Features  
10-Bit Multi-Buffered ADC (MibADC)  
16-Channel  
– Core Supply Voltage (VCC): 1.81 V–2.05 V  
– I/O Supply Voltage (VCCIO): 3.0 V–3.6 V  
– Low-Power Modes: STANDBY and HALT  
– Industrial Temperature Range  
470+ System Module  
– 64-Word FIFO Buffer  
– Single- or Continuous-Conversion Modes  
– 1.55 µs Minimum Sample and Conversion  
Time  
– Calibration Mode and Self-Test Features  
Eight External Interrupts  
– 32-Bit Address Space Decoding  
Flexible Interrupt Handling  
– Bus Supervision for Memory and  
Peripherals  
11 Dedicated GIO Pins, 1 Input-Only GIO Pin,  
and 38 Additional Peripheral I/Os  
– Analog Watchdog (AWD) Timer  
– Real-Time Interrupt (RTI)  
External Clock Prescale (ECP) Module  
– Programmable Low-Frequency External  
Clock (CLK)  
– System Integrity and Failure Detection  
Zero-Pin Phase-Locked Loop (ZPLL)-Based  
Clock Module With Prescaler  
On-Chip Scan-Base Emulation Logic, IEEE  
Standard 1149.1 (1) (JTAG) Boundary-Scan  
Logic  
– Multiply-by-4 or -8 Internal ZPLL Option  
– ZPLL Bypass Mode  
100-Pin Plastic Low-Profile Quad Flatpack (PZ  
Suffix)  
Six Communication Interfaces:  
– Two Serial Peripheral Interfaces (SPIs)  
255 Programmable Baud Rates  
(1) The test-access port is compatible with the IEEE Standard  
1149.1-1990, IEEE Standard Test-Access Port and Boundary  
Scan Architecture. Boundary scan is not supported on this  
device.  
– Two Serial Communications Interfaces  
(SCIs)  
224 Selectable Baud Rates  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ARM7TDMI is a trademark of Advanced RISC Machines (ARM) Limited.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005, Texas Instruments Incorporated  

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