TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
DGC PACKAGE
(TOP VIEW)
Organization . . . 16777216 by 4 Bits
Single 3.3-V Power Supply
(±0.3-V Tolerance)
V
V
SS
1
32
31
30
29
28
27
CC
Performance Ranges:
DQ1
DQ2
NC
NC
NC
NC
W
DQ4
DQ3
NC
2
ACCESS ACCESS ACCESS EDO
3
TIME
TIME
TIME
CYCLE
4
t
t
t
t
HPC
RAC
CAC
AA
NC
5
(MAX)
’46x409/P-40 40 ns
’46x409/P-50 50 ns
’46x409/P-60 60 ns
(MAX)
11 ns
13 ns
15 ns
(MAX)
20 ns
25 ns
30 ns
(MIN)
16 ns
20 ns
25 ns
NC
6
7
26 CAS
8
25
24
23
22
21
20
19
18
17
OE
A12
A11
A10
A9
†
9
RAS
A0
Extended-Data-Out (EDO) Operation
CAS-Before-RAS (CBR) Refresh
10
11
12
13
14
15
16
A1
Long Refresh Period (See Available
Options Table)
A2
A3
A8
Low-Power, Self-Refresh Version
(TMS46x409P)
A4
A7
A5
A6
V
V
3-State Unlatched Output
CC
SS
All Inputs/Outputs and Clocks Are
Low-Voltage TTL (LVTTL) Compatible
†
A12 is NC for TMS465409 and TMS465409P.
High-Reliability Plastic 32-Lead
400-Mil-Wide Thin Small-Outline (TSOP)
Package (DGC Suffix)
PIN NOMENCLATURE
A0–A12
CAS
Address Inputs
Column-Address Strobe
Data In/Data Out
No Internal Connection
Output Enable
Operating Free-Air Temperature Range
DQ1–DQ4
NC
0°C to 70°C
OE
RAS
W
Row-Address Strobe
Write Enable
AVAILABLE OPTIONS
V
3.3-V Supply
Ground
SELF-REFRESH
BATTERY
RAS-ONLY
REFRESH
CYCLES
CBR
REFRESH
CYCLES
CC
V
SS
DEVICE
BACKUP
TMS464409
TMS464409P
TMS465409
TMS465409P
—
YES
—
8192 in 64 ms
4096 in 64 ms
8192 in 128 ms 4096 in 128 ms
4096 in 64 ms 4096 in 64 ms
4096 in 128 ms 4096 in 128 ms
YES
description
The TMS464409 and TMS465409 series are low-voltage, 67108864-bit dynamic random-access memories
(DRAMs), organized as 16777216 words of 4 bits each. The TMS464409P and TMS465409P series are
high-speed, low-voltage, low-power, self-refresh, 67108864-bit DRAMs, organized as 16777216 words of
4 bits each. Both sets of devices employ state-of-the-art technology for high performance, reliability, and low
power.
ThesedevicesfeaturemaximumRASaccesstimesof40, 50, and60ns. Allinputsandoutputs, includingclocks,
are compatible with LVTTL. All addresses and data-in lines are latched on chip to simplify system design. Data
out is unlatched to allow greater system flexibility.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443