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TMS3473BDW-X PDF预览

TMS3473BDW-X

更新时间: 2024-09-16 01:22:11
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德州仪器 - TI 驱动
页数 文件大小 规格书
9页 111K
描述
PARALLEL DRIVER

TMS3473BDW-X 数据手册

 浏览型号TMS3473BDW-X的Datasheet PDF文件第2页浏览型号TMS3473BDW-X的Datasheet PDF文件第3页浏览型号TMS3473BDW-X的Datasheet PDF文件第4页浏览型号TMS3473BDW-X的Datasheet PDF文件第5页浏览型号TMS3473BDW-X的Datasheet PDF文件第6页浏览型号TMS3473BDW-X的Datasheet PDF文件第7页 
TMS3473B  
PARALLEL DRIVER  
SOCS022B – NOVEMBER 1990  
DW PACKAGE  
(TOP VIEW)  
TTL-Compatible Inputs  
CCD-Compatible Outputs  
Variable-Output Slew Rates With External  
Resistor Control  
IALVL  
I/N  
IAIN  
ABIN  
MIDSEL  
SAIN  
PD  
V
SS  
IASR  
ABSR  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
Full-Frame Operation  
Frame-Transfer Operation  
Solid-State Reliability  
Adjustable Clock Levels  
V
CC  
ABLVL  
IAOUT  
ABOUT  
SAOUT  
GND  
description  
V
V
ABG+  
CC  
The TMS3473B is a monolithic CMOS integrated  
V
V
SS  
ABG–  
circuit designed to drive the parallel image-area  
gate (IAG), parallel storage-area gate (SAG), and  
antiblooming gate (ABG) inputs of the Texas Instruments (TI ) virtual-phase CCD image sensors. The  
TMS3473B interfaces the CCD image sensor to a user-defined timing generator; it receives TTL-input signals  
from the timing generator and outputs level-shifted and slew-rate-adjusted signals to the image sensor.  
The TMS3473B allows operation of the CCD image sensor in either the interlace or noninterlace mode. When  
the TMS3473B I/N input is connected to V , the interlace mode is selected (see Figure 1); when I/N is  
SS  
connected to V , the noninterlace mode is selected (see Figure 2).  
CC  
ABOUT follows ABIN and switches between V  
and V  
. IAOUT and SAOUT follow IAIN and SAIN,  
ABG+  
ABG–  
respectively, and switch between V  
and V . Additionally, ABOUT and IAOUT can each be made to output  
CC  
SS  
midlevel voltages. DC inputs to ABLVL and IALVL determine the midlevel voltages that can be output on ABOUT  
and IAOUT, respectively. A high-logic level on MIDSEL causes ABOUT to output its midlevel voltage; a low-logic  
level on MIDSEL causes IAOUT to output its midlevel voltage if the interlace mode is selected.  
Slew-rate adjustment of IAOUT and ABOUT is accomplished by connecting IASR to V  
and ABSR to V  
ABG+  
CC  
through external resistors. The larger the resistor values, the longer the rise and fall times are.  
A low-logic level on PD causes the TMS3473B to power down and all outputs to assume their low levels (IAOUT  
and SAOUT to V , ABOUT to V ).  
SS  
ABG–  
The TMS3473B is supplied in a 20-pin surface-mount package (DW) and is characterized for operation from  
–20°C to 45°C.  
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These  
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,  
Method3015;however, precautionsshouldbetakentoavoidapplicationofanyvoltagehigherthanmaximum-ratedvoltagestothese  
high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in  
conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either V  
Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive  
(ESDS) Devices and Assemblies available from Texas Instruments.  
or ground.  
CC  
TI is a trademark of Texas Instruments Incorporated.  
Copyright 1990, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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