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TMS32C6414DGLZW5E0 PDF预览

TMS32C6414DGLZW5E0

更新时间： 2024-10-27 12:16:07
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
145页 2021K
描述
FIXED-POINT DIGITAL SIGNAL PROCESSORS

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TMS32C6414DGLZW5E0 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：BGA-532针数：532
Reach Compliance Code：compliantECCN代码：3A001.A.3
HTS代码：8542.31.00.01Factory Lead Time：1 week
风险等级：5.64Is Samacsys：N
其他特性：ALSO REQUIRES 3.3VI/O SUPPLY地址总线宽度：32
桶式移位器：NO位大小：32
边界扫描：YES最大时钟频率：75.18 MHz
外部数据总线宽度：64格式：FIXED POINT
内部总线架构：MULTIPLEJESD-30 代码：S-PBGA-B532
JESD-609代码：e0长度：23 mm
低功率模式：YES湿度敏感等级：4
端子数量：532封装主体材料：PLASTIC/EPOXY
封装代码：HFBGA封装等效代码：BGA532,26X26,32
封装形状：SQUARE封装形式：GRID ARRAY, HEAT SINK/SLUG, FINE PITCH
峰值回流温度（摄氏度）：220电源：1.2,3.3 V
认证状态：Not QualifiedRAM（字数）：4096
座面最大高度：3.3 mm子类别：Digital Signal Processors
最大供电电压：1.26 V最小供电电压：1.14 V
标称供电电压：1.2 V表面贴装：YES
技术：CMOS端子面层：TIN LEAD
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：23 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

TMS32C6414DGLZW5E0 数据手册

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TMS320C6414, TMS320C6415, TMS320C6416  
FIXED-POINT DIGITAL SIGNAL PROCESSORS  
SPRS146N − FEBRUARY 2001 − REVISED MAY 2005  
ꢀ
Highest-Performance Fixed-Point Digital  
Signal Processors (DSPs)  
− 2-, 1.67-, 1.39-ns Instruction Cycle Time  
− 500-, 600-, 720-MHz Clock Rate  
− Eight 32-Bit Instructions/Cycle  
− Twenty-Eight Operations/Cycle  
− 4000, 4800, 5760 MIPS  
ꢀ
Two External Memory Interfaces (EMIFs)  
− One 64-Bit (EMIFA), One 16-Bit (EMIFB)  
− Glueless Interface to Asynchronous  
Memories (SRAM and EPROM) and  
Synchronous Memories (SDRAM,  
SBSRAM, ZBT SRAM, and FIFO)  
− 1280M-Byte Total Addressable External  
Memory Space  
− Fully Software-Compatible With C62x™  
− C6414/15/16 Devices Pin-Compatible  
ꢀ
ꢀ
ꢀ
Enhanced Direct-Memory-Access (EDMA)  
Controller (64 Independent Channels)  
ꢀ
VelociTI.2™ Extensions to VelociTI™  
Advanced Very-Long-Instruction-Word  
(VLIW) TMS320C64x™ DSP Core  
− Eight Highly Independent Functional  
Units With VelociTI.2™ Extensions:  
− Six ALUs (32-/40-Bit), Each Supports  
Single 32-Bit, Dual 16-Bit, or Quad  
8-Bit Arithmetic per Clock Cycle  
− Two Multipliers Support  
Host-Port Interface (HPI)  
− User-Configurable Bus Width (32-/16-Bit)  
32-Bit/33-MHz, 3.3-V PCI Master/Slave  
Interface Conforms to PCI Specification 2.2  
[C6415/C6416 ]  
− Three PCI Bus Address Registers:  
Prefetchable Memory  
Non-Prefetchable Memory I/O  
− Four-Wire Serial EEPROM Interface  
− PCI Interrupt Request Under DSP  
Program Control  
Four 16 x 16-Bit Multiplies  
(32-Bit Results) per Clock Cycle or  
Eight 8 x 8-Bit Multiplies  
(16-Bit Results) per Clock Cycle  
− Non-Aligned Load-Store Architecture  
− 64 32-Bit General-Purpose Registers  
− Instruction Packing Reduces Code Size  
− All Instructions Conditional  
− DSP Interrupt Via PCI I/O Cycle  
ꢀ
Three Multichannel Buffered Serial Ports  
− Direct I/F to T1/E1, MVIP, SCSA Framers  
− Up to 256 Channels Each  
− ST-Bus-Switching-, AC97-Compatible  
− Serial Peripheral Interface (SPI)  
Compatible (Motorola™)  
ꢀ
Instruction Set Features  
− Byte-Addressable (8-/16-/32-/64-Bit Data)  
− 8-Bit Overflow Protection  
− Bit-Field Extract, Set, Clear  
− Normalization, Saturation, Bit-Counting  
− VelociTI.2™ Increased Orthogonality  
Viterbi Decoder Coprocessor (VCP) [C6416]  
− Supports Over 600 7.95-Kbps AMR  
− Programmable Code Parameters  
ꢀ
ꢀ
Three 32-Bit General-Purpose Timers  
Universal Test and Operations PHY  
Interface for ATM (UTOPIA) [C6415/C6416]  
− UTOPIA Level 2 Slave ATM Controller  
− 8-Bit Transmit and Receive Operations  
up to 50 MHz per Direction  
ꢀ
ꢀ
− User-Defined Cell Format up to 64 Bytes  
Turbo Decoder Coprocessor (TCP) [C6416]  
− Supports up to 7 2-Mbps or  
43 384-Kbps 3GPP (6 Iterations)  
− Programmable Turbo Code and  
Decoding Parameters  
ꢀ
ꢀ
ꢀ
Sixteen General-Purpose I/O (GPIO) Pins  
Flexible PLL Clock Generator  
†
IEEE-1149.1 (JTAG )  
Boundary-Scan-Compatible  
ꢀ
L1/L2 Memory Architecture  
− 128K-Bit (16K-Byte) L1P Program Cache  
(Direct Mapped)  
− 128K-Bit (16K-Byte) L1D Data Cache  
(2-Way Set-Associative)  
− 8M-Bit (1024K-Byte) L2 Unified Mapped  
RAM/Cache (Flexible Allocation)  
ꢀ
532-Pin Ball Grid Array (BGA) Package  
(GLZ, ZLZ and CLZ Suffixes), 0.8-mm Ball  
Pitch  
ꢀ
ꢀ
ꢀ
0.13-µm/6-Level Cu Metal Process (CMOS)  
3.3-V I/Os, 1.2-V/1.25-V Internal (500 MHz)  
3.3-V I/Os, 1.4-V Internal (600 and 720 MHz)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.  
Motorola is a trademark of Motorola, Inc.  
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright © 2005 Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...145

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