TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
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200-MIPS Dual-Core DSP Consisting of Two
Independent Subsystems
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Arithmetic Instructions With Parallel Store
and Parallel Load
Each Core Has an Advanced Multibus
Architecture With Three Separate 16-Bit
Data Memory Buses and One Program Bus
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Conditional Store Instructions
Output Control of CLKOUT
Output Control of TOUT
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40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel-Shifter and Two
40-Bit Accumulators Per Core
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions
Dual 1.8-V (Core) and 3.3-V (I/O) Power
Supplies for Low Power, Fast Operation
Each Core Has a 17- × 17-Bit Parallel
Multiplier Coupled to a 40-Bit Adder for
Non-Pipelined Single-Cycle Multiply/
Accumulate (MAC) Operations
10-ns Single-Cycle Fixed-Point Instruction
Execution
Interprocessor Communication via Two
Internal 8-Element FIFOs
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Each Core Has a Compare, Select, and
Store Unit (CSSU) for the Add/Compare
Selection of the Viterbi Operator
12 Channels of Direct Memory Access
(DMA) for Data Transfers With No CPU
Loading (6 Channels Per Subsystem)
Each Core Has an Exponent Encoder to
Compute an Exponent Value of a 40-Bit
Accumulator Value in a Single Cycle
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Six Multichannel Buffered Serial Ports
(McBSPs) (Three McBSPs Per Subsystem)
Each Core Has Two Address Generators
With Eight Auxiliary Registers and Two
Auxiliary Register Arithmetic Units
(ARAUs)
16-Bit Host-Port Interface (HPI16)
Multiplexed With External Memory Interface
Pins
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Software-Programmable Phase-Locked
Loop (PLL) Provides Several Clocking
Options (Requires External TTL Oscillator)
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16-Bit Data Bus With Data Bus Holder
Feature
256K × 16 Extended Program Address
Space
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On-Chip Scan-Based Emulation Logic
Total of 200K × 16 Dual- and Single-Access
On-Chip RAM
Two Software-Programmable Timers
(One Per Subsystem)
Single-Instruction Repeat and
Block-Repeat Operations
Software-Programmable Wait-State
Generator (14 Wait States Maximum)
Instructions With 32-Bit Long Word
Operands
Provided in 144-pin BGA Ball Grid Array
(GGU Suffix) and 144-pin Thin Quad
Flatpack (TQFP) (PGE Suffix) packages
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Instructions With 2 or 3 Operand Reads
Fast Return From Interrupts
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NOTE:This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview
(literature number SPRU307).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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