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TMS320VC5402GGU PDF预览

TMS320VC5402GGU

更新时间： 2024-10-26 22:11:51
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
68页 939K
描述
FIXED-POINT DIGITAL SIGNAL PROCESSOR

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TMS320VC5402GGU 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：BGA包装说明：LFBGA, BGA144,13X13,32
针数：144Reach Compliance Code：not_compliant
风险等级：5.66Is Samacsys：N
其他特性：ALSO REQUIRES 3.3V SUPPLY地址总线宽度：20
桶式移位器：YES位大小：16
边界扫描：YES最大时钟频率：20 MHz
外部数据总线宽度：16格式：FIXED POINT
内部总线架构：MULTIPLEJESD-30 代码：S-PBGA-B144
长度：12 mm低功率模式：YES
端子数量：144最高工作温度：100 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装等效代码：BGA144,13X13,32
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.8,3.3 V
认证状态：Not QualifiedRAM（字数）：16384
座面最大高度：1.4 mm子类别：Digital Signal Processors
最大供电电压：1.98 V最小供电电压：1.71 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：12 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

TMS320VC5402GGU 数据手册

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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000  
D
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Advanced Multibus Architecture With Three  
Separate 16-Bit Data Memory Buses and  
One Program Memory Bus  
D
D
D
D
Arithmetic Instructions With Parallel Store  
and Parallel Load  
Conditional Store Instructions  
Fast Return From Interrupt  
40-Bit Arithmetic Logic Unit (ALU),  
Including a 40-Bit Barrel Shifter and Two  
Independent 40-Bit Accumulators  
On-Chip Peripherals  
– Software-Programmable Wait-State  
Generator and Programmable Bank  
Switching  
– On-Chip Phase-Locked Loop (PLL) Clock  
Generator With Internal Oscillator or  
External Clock Source  
– Two Multichannel Buffered Serial Ports  
(McBSPs)  
– Enhanced 8-Bit Parallel Host-Port  
Interface (HPI8)  
17- × 17-Bit Parallel Multiplier Coupled to a  
40-Bit Dedicated Adder for Non-Pipelined  
Single-Cycle Multiply/Accumulate (MAC)  
Operation  
D
D
D
Compare, Select, and Store Unit (CSSU) for  
the Add/Compare Selection of the Viterbi  
Operator  
Exponent Encoder to Compute an  
Exponent Value of a 40-Bit Accumulator  
Value in a Single Cycle  
– Two 16-Bit Timers  
– Six-Channel Direct Memory Access  
(DMA) Controller  
Two Address Generators With Eight  
Auxiliary Registers and Two Auxiliary  
Register Arithmetic Units (ARAUs)  
D
Power Consumption Control With IDLE1,  
IDLE2, and IDLE3 Instructions With  
Power-Down Modes  
D
D
Data Bus With a Bus-Holder Feature  
Extended Addressing Mode for 1M × 16-Bit  
Maximum Addressable External Program  
Space  
D
D
CLKOUT Off Control to Disable CLKOUT  
On-Chip Scan-Based Emulation Logic,  
†
IEEE Std 1149.1 (JTAG) Boundary Scan  
D
D
D
D
D
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4K x 16-Bit On-Chip ROM  
Logic  
16K x 16-Bit Dual-Access On-Chip RAM  
D
D
10-ns Single-Cycle Fixed-Point Instruction  
Execution Time (100 MIPS) for 3.3-V Power  
Supply (1.8-V Core)  
Single-Instruction-Repeat and  
Block-Repeat Operations for Program Code  
Block-Memory-Move Instructions for  
Efficient Program and Data Management  
Available in a 144-Pin Plastic Low-Profile  
Quad Flatpack (LQFP) (PGE Suffix) and a  
144-Pin Ball Grid Array (BGA) (GGU Suffix)  
Instructions With a 32-Bit Long Word  
Operand  
Instructions With Two- or Three-Operand  
Reads  
NOTE:This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview  
(literature number SPRU307).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 2000, Texas Instruments Incorporated  
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...68

中文翻译

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