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SPRS218I − MAY 2003 − REVISED APRIL 2009
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Highest-Performance Fixed-Point Digital
Signal Processors (DSPs)
− 1.67-, 1.39-ns Instruction Cycle Time
− 600-, 720-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− Twenty-Eight Operations/Cycle
− 4800, 5760 MIPS
− Fully Software-Compatible With C62x
− TCI100/C6416 Pin-Compatible
− Extended Temperature Devices Available
− 8M-Bit (1024K-Byte) L2 Unified Mapped
RAM/Cache (Flexible Allocation)
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Two External Memory Interfaces (EMIFs)
− One 64-Bit (EMIFA), One 16-Bit (EMIFB)
− Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
− 1280M-Byte Total Addressable External
Memory Space
VelociTI.2 Extensions to VelociTI
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x DSP Core
− Eight Highly Independent Functional
Units With VelociTI.2 Extensions:
− Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
− Two Multipliers Support
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Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
Host-Port Interface (HPI)
− User-Configurable Bus Width (32-/16-Bit)
32-Bit/33-MHz, 3.3-V PCI Master/Slave
Interface Conforms to PCI Specification 2.2
− Three PCI Bus Address Registers:
Prefetchable Memory
Non-Prefetchable Memory I/O
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
− Four-Wire Serial EEPROM Interface
− PCI Interrupt Request Under DSP
Program Control
(16-Bit Results) per Clock Cycle
− Non-Aligned Load-Store Architecture
− 64 32-Bit General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
− DSP Interrupt Via PCI I/O Cycle
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Three Multichannel Buffered Serial Ports
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− Up to 256 Channels Each
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Instruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data)
− 8-Bit Overflow Protection
− ST-Bus-Switching-, AC97-Compatible
− Serial Peripheral Interface (SPI)
Compatible (Motorola)
− Bit-Field Extract, Set, Clear
− Normalization, Saturation, Bit-Counting
− VelociTI.2 Increased Orthogonality
VCP
− Supports Over 600 7.95-Kbps AMR
− Programmable Code Parameters
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Three 32-Bit General-Purpose Timers
UTOPIA
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− UTOPIA Level 2 Slave ATM Controller
− 8-Bit Transmit and Receive Operations
up to 50 MHz per Direction
− User-Defined Cell Format up to 64 Bytes
TCP
− Supports up to Seven 2-Mbps 3GPP
(6 Iterations)
− Programmable Turbo Code and
Decoding Parameters
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Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
†
IEEE-1149.1 (JTAG )
Boundary-Scan-Compatible
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L1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
− 128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
532-Pin Ball Grid Array (BGA) Package
(GLZ, ZLZ, CLZ Suffixes), 0.8-mm Ball Pitch
0.09-µm/7-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.1-V Internal (600 MHz)
3.3-V I/Os, 1.2-V Internal (720 MHz)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
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Copyright 2009, Texas Instruments Incorporated
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