TMS320DM6433
Digital Media Processor
www.ti.com
SPRS343C–NOVEMBER 2006–REVISED JUNE 2008
1 TMS320DM6433 Digital Media Processor
1.1 Features
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256K-Bit (32K-Byte) L1P Program
RAM/Cache [Flexible Allocation]
640K-Bit (80K-Byte) L1D Data RAM/Cache
[Flexible Allocation]
1M-Bit (128K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
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High-Performance Digital Media Processor
(DM6433)
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2.5-, 2-, 1.67-, 1.51-, 1.43-ns ns Instruction
Cycle Time
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400-, 500, -600-, 660-, 700-MHz C64x+™
Clock Rate
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Supports Little Endian Mode Only
Video Processing Subsystem (VPSS)
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Eight 32-Bit C64x+ Instructions/Cycle
3200, 4000, 4800, 5280, 5600 MIPS
Fully Software-Compatible With C64x
Commercial and Automotive (Q or S suffix)
Grades
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Front End Provides (Resizer Only):
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Resize Images From 1/4x to 4x
Separate Horizontal and Vertical Control
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Low-Power Device (L suffix)
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Back End Provides:
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VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
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Hardware On-Screen Display (OSD)
Four 54-MHz DACs for a Combination of
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Composite NTSC/PAL Video
Luma/Chroma Separate Video
(S-video)
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Eight Highly Independent Functional Units
With VelociTI.2 Extensions:
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Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
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Component (YPbPr or RGB) Video
(Progressive)
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Digital Output
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Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
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8-/16-bit YUV or up to 24-Bit RGB
HD Resolution
Up to 2 Video Windows
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External Memory Interfaces (EMIFs)
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Load-Store Architecture With Non-Aligned
Support
64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
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32-Bit DDR2 SDRAM Memory Controller
With 256M-Byte Address Space (1.8-V I/O)
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Supports up to 333-MHz (data rate) bus
and interfaces to DDR2-400 SDRAM
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Asynchronous 8-Bit Wide EMIF (EMIFA)
With up to 64M-Byte Address Reach
Additional C64x+™ Enhancements
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Protected Mode Operation
Exceptions Support for Error Detection
and Program Redirection
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Flash Memory Interfaces
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NOR (8-Bit-Wide Data)
NAND (8-Bit-Wide Data)
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Hardware Support for Modulo Loop
Auto-Focus Module Operation
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Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
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C64x+ Instruction Set Features
Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
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Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation, Bit-Counting
VelociTI.2 Increased Orthogonality
C64x+ Extensions
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One 64-Bit Watch Dog Timer
One UART With RTS and CTS Flow Control
Master/Slave Inter-Integrated Circuit (I2C
Bus™)
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Compact 16-bit Instructions
Additional Instructions to Support
Complex Multiplies
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One Multichannel Buffered Serial Port
(McBSP0)
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I2S and TDM
AC97 Audio Codec Interface
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C64x+ L1/L2 Memory Architecture
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