TMS320C6742 Fixed/Floating-Point DSP
www.ti.com
SPRS587–JUNE 2009
1 TMS320C6742 Fixed/Floating-Point DSP
1.1 Features
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Fixed Point Multiply Supports Two 32 x
32-Bit Multiplies, Four 16 x 16-Bit
Multiplies, or Eight 8 x 8-Bit Multiplies
per Clock Cycle, and Complex Multiples
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300-MHz C674x VLIW DSP
C674x Instruction Set Features
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Superset of the C67x+™ and C64x+™ ISAs
2400/1800 C674x MIPS/MFLOPS
Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation, Bit-Counting
Compact 16-Bit Instructions
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Instruction Packing Reduces Code Size
All Instructions Conditional
Hardware Support for Modulo Loop
Operation
Protected Mode Operation
Exceptions Support for Error Detection and
Program Redirection
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C674x Two Level Cache Memory Architecture
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Software Support
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32K-Byte L1P Program RAM/Cache
32K-Byte L1D Data RAM/Cache
64K-Byte L2 Unified Mapped RAM/Cache
Flexible RAM/Cache Partition (L1 and L2)
1024K-Byte Boot ROM
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TI DSP/BIOS™
Chip Support Library and DSP Library
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1.8V or 3.3V LVCMOS IOs (except DDR2
interfaces)
Enhanced Direct-Memory-Access Controller 3
(EDMA3):
Two External Memory Interfaces:
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EMIFA
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2 Channel Controllers
3 Transfer Controllers
64 Independent DMA Channels
16 Quick DMA Channels
Programmable Transfer Burst Size
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NOR (8-/16-Bit-Wide Data)
NAND (8-/16-Bit-Wide Data)
16-Bit SDRAM With 128 MB Address
Space
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DDR2/Mobile DDR Memory Controller
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16-Bit DDR2 SDRAM With 512 MB
Address Space or
16-Bit mDDR SDRAM With 256 MB
Address Space
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TMS320C674x Floating-Point VLIW DSP Core
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Load-Store Architecture With Non-Aligned
Support
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64 General-Purpose Registers (32 Bit)
Six ALU (32-/40-Bit) Functional Units
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One Configurable 16550 type UART Modules:
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With Modem Control Signals
16-byte FIFO
16x or 13x Oversampling Option
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Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
Supports up to Four SP Additions Per
Clock, Four DP Additions Every 2
Clocks
Supports up to Two Floating Point (SP
or DP) Reciprocal Approximation
(RCPxP) and Square-Root Reciprocal
Approximation (RSQRxP) Operations
Per Cycle
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One Serial Peripheral Interface (SPI) With
Multiple Chip-Selects
One Master/Slave Inter-Integrated Circuit (I2C
Bus™)
One Multichannel Audio Serial Port:
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Transmit/Receive Clocks up to 50 MHz
Two Clock Zones and 16 Serial Data Pins
Supports TDM, I2S, and Similar Formats
DIT-Capable
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Two Multiply Functional Units
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Mixed-Precision IEEE Floating Point
Multiply Supported up to:
FIFO buffers for Transmit and Receive
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2 SP x SP -> SP Per Clock
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One Multichannel Buffered Serial Ports:
2 SP x SP -> DP Every Two Clocks
2 SP x DP -> DP Every Three Clocks
2 DP x DP -> DP Every Four Clocks
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Transmit/Receive Clocks up to 50 MHz
Two Clock Zones and 16 Serial Data Pins
Supports TDM, I2S, and Similar Formats
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Instruments semiconductor products and disclaimers thereto appears at the end of this document.
TMS320C6000, C6000 are trademarks of Texas Instruments.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2009, Texas Instruments Incorporated