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TMS320C6211BGFN167 PDF预览

TMS320C6211BGFN167

更新时间: 2024-10-26 22:32:39
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
83页 1163K
描述
FIXED-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6211BGFN167 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:BGA包装说明:BGA-256
针数:256Reach Compliance Code:not_compliant
ECCN代码:3A001.A.3HTS代码:8542.31.00.01
Factory Lead Time:1 week风险等级:5.46
Is Samacsys:N其他特性:ALSO REQUIRES 3.3V I/O SUPPLY
地址总线宽度:22桶式移位器:NO
位大小:32边界扫描:YES
最大时钟频率:167 MHz外部数据总线宽度:32
格式:FIXED POINT内部总线架构:MULTIPLE
JESD-30 代码:S-PBGA-B256JESD-609代码:e0
长度:27 mm低功率模式:YES
湿度敏感等级:4端子数量:256
最高工作温度:90 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA256,20X20,50封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):220
电源:1.8,3.3 V认证状态:Not Qualified
RAM(字数):4096座面最大高度:2.32 mm
子类别:Digital Signal Processors最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:27 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

TMS320C6211BGFN167 数据手册

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TMS320C6211, TMS320C6211B  
FIXED-POINT DIGITAL SIGNAL PROCESSORS  
SPRS073K AUGUST 1998 REVISED MARCH 2004  
D
D
Excellent Price/Performance Digital Signal  
Processors (DSPs): TMS320C62x  
(TMS320C6211 and TMS320C6211B)  
Eight 32-Bit Instructions/Cycle  
C6211, C6211B, C6711, and C6711B are  
Pin-Compatible  
150-, 167-MHz Clock Rates  
6.7-, 6-ns Instruction Cycle Time  
1200, 1333 MIPS  
D
D
Device Configuration  
Boot Mode: HPI, 8-, 16-, and 32-Bit ROM  
Boot  
Endianness: Little Endian, Big Endian  
32-Bit External Memory Interface (EMIF)  
Glueless Interface to Asynchronous  
Memories: SRAM and EPROM  
Glueless Interface to Synchronous  
Memories: SDRAM and SBSRAM  
512M-Byte Total Addressable External  
Memory Space  
Extended Temperature Device (C6211B)  
VelociTIAdvanced Very Long Instruction  
Word (VLIW) C62xDSP Core (C6211/11B)  
Eight Highly Independent Functional  
Units:  
D
D
D
Enhanced Direct-Memory-Access (EDMA)  
Controller (16 Independent Channels)  
16-Bit Host-Port Interface (HPI)  
Access to Entire Memory Map  
Six ALUs (32-/40-Bit)  
Two 16-Bit Multipliers (32-Bit Results)  
Load-Store Architecture With 32 32-Bit  
General-Purpose Registers  
Instruction Packing Reduces Code Size  
All Instructions Conditional  
Two Multichannel Buffered Serial Ports  
(McBSPs)  
Direct Interface to T1/E1, MVIP, SCSA  
Framers  
ST-Bus-Switching Compatible  
Up to 256 Channels Each  
AC97-Compatible  
Serial-Peripheral-Interface (SPI)  
Compatible (Motorola)  
D
D
Instruction Set Features  
Byte-Addressable (8-, 16-, 32-Bit Data)  
8-Bit Overflow Protection  
Saturation  
Bit-Field Extract, Set, Clear  
Bit-Counting  
D
D
Two 32-Bit General-Purpose Timers  
Normalization  
Flexible Phase-Locked-Loop (PLL) Clock  
Generator  
L1/L2 Memory Architecture  
32K-Bit (4K-Byte) L1P Program Cache  
(Direct Mapped)  
32K-Bit (4K-Byte) L1D Data Cache  
(2-Way Set-Associative)  
512K-Bit (64K-Byte) L2 Unified Mapped  
RAM/Cache  
D
D
D
D
IEEE-1149.1 (JTAG )  
Boundary-Scan-Compatible  
256-Pin Ball Grid Array (BGA) Package  
(GFN Suffix)  
0.18-µm/5-Level Metal Process  
CMOS Technology  
(Flexible Data/Program Allocation)  
3.3-V I/Os, 1.8-V Internal  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.  
Motorola is a trademark of Motorola, Inc.  
All trademarks are the property of their respective owners.  
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 2004, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443  

TMS320C6211BGFN167 替代型号

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