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TMS320C5420PGEA200 PDF预览

TMS320C5420PGEA200

更新时间： 2024-01-22 16:57:19
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
82页 1124K
描述
FIXED-POINT DIGITAL SIGNAL PROCESSOR

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TMS320C5420PGEA200 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP-144
针数：144Reach Compliance Code：compliant
ECCN代码：3A991.A.2HTS代码：8542.31.00.01
Factory Lead Time：1 week风险等级：5.8
Is Samacsys：N其他特性：ALSO REQUIRES 3.3V SUPPLY
地址总线宽度：18桶式移位器：YES
位大小：16边界扫描：YES
最大时钟频率：100 MHz外部数据总线宽度：16
格式：FIXED POINT内部总线架构：MULTIPLE
JESD-30 代码：S-PQFP-G144JESD-609代码：e4
长度：20 mm低功率模式：YES
湿度敏感等级：1端子数量：144
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP144,.87SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：1.8,3.3 V认证状态：Not Qualified
RAM（字数）：65536座面最大高度：1.6 mm
子类别：Digital Signal Processors最大供电电压：1.98 V
最小供电电压：1.71 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：20 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

TMS320C5420PGEA200 数据手册

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SPRS080F − MARCH 1999 − REVISED OCTOBER 2008  
D
D
200-MIPS Dual-Core DSP Consisting of Two  
Independent Subsystems  
D
Arithmetic Instructions With Parallel Store  
and Parallel Load  
Each Core Has an Advanced Multibus  
Architecture With Three Separate 16-Bit  
Data Memory Buses and One Program Bus  
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Conditional Store Instructions  
Output Control of CLKOUT  
Output Control of TOUT  
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40-Bit Arithmetic Logic Unit (ALU)  
Including a 40-Bit Barrel-Shifter and Two  
40-Bit Accumulators Per Core  
Power Consumption Control With IDLE1,  
IDLE2, and IDLE3 Instructions  
Dual 1.8-V (Core) and 3.3-V (I/O) Power  
Supplies for Low Power, Fast Operation  
Each Core Has a 17- × 17-Bit Parallel  
Multiplier Coupled to a 40-Bit Adder for  
Non-Pipelined Single-Cycle Multiply/  
Accumulate (MAC) Operations  
10-ns Single-Cycle Fixed-Point Instruction  
Execution  
Interprocessor Communication via Two  
Internal 8-Element FIFOs  
D
D
D
Each Core Has a Compare, Select, and  
Store Unit (CSSU) for the Add/Compare  
Selection of the Viterbi Operator  
12 Channels of Direct Memory Access  
(DMA) for Data Transfers With No CPU  
Loading (6 Channels Per Subsystem)  
Each Core Has an Exponent Encoder to  
Compute an Exponent Value of a 40-Bit  
Accumulator Value in a Single Cycle  
D
D
Six Multichannel Buffered Serial Ports  
(McBSPs) (Three McBSPs Per Subsystem)  
Each Core Has Two Address Generators  
With Eight Auxiliary Registers and Two  
Auxiliary Register Arithmetic Units  
(ARAUs)  
16-Bit Host-Port Interface (HPI16)  
Multiplexed With External Memory Interface  
Pins  
D
Software-Programmable Phase-Locked  
Loop (PLL) Provides Several Clocking  
Options (Requires External TTL Oscillator)  
D
D
D
D
D
16-Bit Data Bus With Data Bus Holder  
Feature  
256K × 16 Extended Program Address  
Space  
D
D
D
D
On-Chip Scan-Based Emulation Logic  
Total of 192K × 16 Dual- and Single-Access  
On-Chip RAM  
Two Software-Programmable Timers  
(One Per Subsystem)  
Single-Instruction Repeat and  
Block-Repeat Operations  
Software-Programmable Wait-State  
Generator (14 Wait States Maximum)  
Instructions With 32-Bit Long Word  
Operands  
Provided in 144-pin BGA Ball Grid Array  
(GGU Suffix) and 144-pin Low-Profile Quad  
Flatpack (LQFP) (PGE Suffix) Packages  
D
Instructions With 2 or 3 Operand Reads  
Fast Return From Interrupts  
D
NOTE: This data sheet is designed to be used in conjunction with the TMS320C54xDSP Functional Overview (literature  
number SPRU307).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TMS320C54x is a trademark of Texas Instruments.  
All trademarks are the property of their respective owners.  
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Copyright 2008, Texas Instruments Incorporated  
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1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...82

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