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TMS320C25FNLW PDF预览

TMS320C25FNLW

更新时间: 2024-11-25 23:14:51
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
69页 598K
描述
SECOND-GENERATION DIGITAL SIGNAL PROCESSORS

TMS320C25FNLW 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:LCC
包装说明:GREEN, PLASTIC, LCC-68针数:68
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.65
Is Samacsys:N地址总线宽度:16
桶式移位器:NO位大小:16
边界扫描:NO最大时钟频率:40.96 MHz
外部数据总线宽度:16格式:FIXED POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PQCC-J68
JESD-609代码:e4长度:24.23 mm
低功率模式:YES湿度敏感等级:3
端子数量:68最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC68,1.0SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not QualifiedRAM(字数):544
座面最大高度:4.57 mm子类别:Digital Signal Processors
最大压摆率:360 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:24.23 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

TMS320C25FNLW 数据手册

 浏览型号TMS320C25FNLW的Datasheet PDF文件第2页浏览型号TMS320C25FNLW的Datasheet PDF文件第3页浏览型号TMS320C25FNLW的Datasheet PDF文件第4页浏览型号TMS320C25FNLW的Datasheet PDF文件第5页浏览型号TMS320C25FNLW的Datasheet PDF文件第6页浏览型号TMS320C25FNLW的Datasheet PDF文件第7页 
TMS320 SECOND-GENERATION  
DIGITAL SIGNAL PROCESSORS  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
68-Pin GB Package  
(Top View)  
80-ns Instruction Cycle Time  
1
2 3 4 5 6 7 8 9 10 11  
544 Words of On-Chip Data RAM  
4K Words of On-Chip Secure Program  
EPROM (TMS320E25)  
A
B
C
D
E
F
4K Words of On-Chip Program ROM  
(TMS320C25)  
128K Words of Data/Program Space  
32-Bit ALU/Accumulator  
G
H
J
16 × 16-Bit Multiplier With a 32-Bit Product  
Block Moves for Data/Program  
Management  
K
L
Repeat Instructions for Efficient Use of  
Program Space  
68-Pin FN and FZ Packages  
(Top View)  
Serial Port for Direct Codec Interface  
Synchronization Input for Synchronous  
Multiprocessor Configurations  
Wait States for Communication to Slow  
Off-Chip Memories/Peripherals  
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61  
60  
59  
V
IACK  
MSC  
10  
SS  
D7  
D6  
D5  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
58 CLKOUT1  
57 CLKOUT2  
56 XF  
On-Chip Timer for Control Operations  
Single 5-V Supply  
D4  
D3  
D2  
D1  
D0  
55 HOLDA  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
DX  
Packaging: 68-Pin PGA, PLCC, and  
CER-QUAD  
FSX  
X2 CLKIN  
X1  
SYNC  
INT0  
INT1  
INT2  
BR  
68-to-28 Pin Conversion Adapter Socket for  
EPROM Programming  
STRB  
R/W  
PS  
IS  
DS  
V
DR  
CC  
Commercial and Military Versions Available  
FSR  
NMOS Technology:  
— TMS32020 . . . . . . . . . 200-ns cycle time  
A0 26  
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43  
V
SS  
CMOS Technology:  
— TMS320C25 . . . . . . . . 100-ns cycle time  
— TMS320E25 . . . . . . . . 100-ns cycle time  
— TMS320C25-50 . . . . . . 80-ns cycle time  
description  
This data sheet provides complete design documentation for the second-generation devices of the TMS320  
family. This facilitates the selection of the devices best suited for user applications by providing all specifications  
and special features for each TMS320 member. This data sheet is divided into four major sections: architecture,  
electrical specifications (NMOS and CMOS), timing diagrams, and mechanical data. In each of these sections,  
generic information is presented first, followed by specific device information. An index is provided for quick  
reference to specific information about a device.  
ADVANCE INFORMATION concerns new products in the  
Copyright 1991, Texas Instruments Incorporated  
sampling or preproduction phase of development.  
Characteristic data and other specifications are subject to  
change without notice.  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  
1

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