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TMS29F800T-100BDBJL PDF预览

TMS29F800T-100BDBJL

更新时间： 2024-11-07 22:06:11
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德州仪器 - TI 闪存
页数 文件大小 规格书
51页 684K
描述
1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES

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TMS29F800T-100BDBJL 数据手册

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TMS29F800T, TMS29F800B  
1048576 BY 8-BIT/524288 BY 16-BIT  
FLASH MEMORIES  
SMJS835B – MAY 1997 – REVISED OCTOBER 1997  
Single Power Supply Supports 5 V 10%  
Read/Write Operation  
Erase Suspend/Resume  
– Supports Reading Data From, or  
Programming Data to, a Sector Not  
Being Erased  
Organization . . . 1048576 By 8 Bits  
524288 By 16 Bits  
Hardware-Reset Pin Initializes the  
Internal-State Machine to the Read  
Operation  
Array-Blocking Architecture  
– One 16K-Byte/One 8K-Word Boot Sector  
– Two 8K-Byte/4K-Word Parameter Sectors  
– One 32K-Byte/16K-Word Sector  
– Fifteen 64K-Byte/32K-Word Sectors  
– Any Combination of Sectors Can Be  
Erased. Supports Full-Chip Erase  
– Any Combination of Sectors Can Be  
Marked as Read-Only  
Package Options  
– 44-Pin Plastic Small-Outline Package  
(PSOP) (DBJ Suffix)  
– 48-Pin Thin Small-Outline Package  
(TSOP) (DCD Suffix)  
Detection Of Program/Erase Operation  
– Data Polling and Toggle Bit Feature of  
Program/Erase Cycle Completion  
Boot-Code Sector Architecture  
– T = Top Sector  
– B = Bottom Sector  
– Hardware Method for Detection of  
Program/Erase Cycle Completion  
Sector Protection  
Through Ready/Busy (RY/BY) Output Pin  
– Hardware Protection Method That  
Disables Any Combination of Sectors  
From Write or Erase Operations Using  
Standard Programming Equipment  
High-Speed Data Access at 5-V V  
at Three Temperature Ranges  
10%  
CC  
– 80 ns  
– 90 ns  
– 100 ns  
– 120 ns  
Commercial . . . 0°C to 70°C  
Commercial . . . 0°C to 70°C  
Extended . . . –40°C to 85°C  
Automotive . . . –40°C to 125°C  
Embedded Program/Erase Algorithms  
– Automatically Pre-Programs and Erases  
Any Sector  
– Automatically Programs and Verifies the  
Program Data at Specified Address  
PIN NOMENCLATURE  
JEDEC Standards  
– Compatible With JEDEC Byte Pinouts  
– Compatible With JEDEC EEPROM  
Command Set  
A[0:18]  
BYTE  
Address Inputs  
Byte/Word Enable  
Data In/Data out  
DQ[0:14]  
DQ15/A  
–1  
Data In/Out (Word-Wide Mode)  
Low-Order Address (Byte-Wide Mode)  
Chip Enable  
Fully Automated On-Chip Erase and  
Program Operations  
CE  
100 000 Program/Erase Cycles  
OE  
Output Enable  
Low Power Dissipation  
NC  
No Internal Connection  
Reset/Deep Power Down  
Ready/Busy Output  
Power Supply  
– 40-mA Typical Active Read for Byte Mode  
– 50-mA Typical Active Read for Word  
Mode  
– 60-mA Typical Program/Erase Current  
– Less Than 100-µA Standby Current  
– 5 µA in Deep Power-Down Mode  
RESET  
RY/BY  
V
V
CC  
Ground  
SS  
WE  
Write Enable  
All Inputs/Outputs TTL-Compatible  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...51

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