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TMS28F400AFT60CDBJL PDF预览

TMS28F400AFT60CDBJL

更新时间： 2024-11-13 05:03:47
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德州仪器 - TI 闪存
页数 文件大小 规格书
80页 1094K
描述
524288 BY 8-BIT/262144 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

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TMS28F400AFT60CDBJL 数据手册

 浏览型号TMS28F400AFT60CDBJL的Datasheet PDF文件第2页浏览型号TMS28F400AFT60CDBJL的Datasheet PDF文件第3页浏览型号TMS28F400AFT60CDBJL的Datasheet PDF文件第4页浏览型号TMS28F400AFT60CDBJL的Datasheet PDF文件第5页浏览型号TMS28F400AFT60CDBJL的Datasheet PDF文件第6页浏览型号TMS28F400AFT60CDBJL的Datasheet PDF文件第7页 
TMS28F004Axy, TMS28F400Axy  
524288 BY 8-BIT/262144 BY 16-BIT  
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES  
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997  
DBJ PACKAGE  
(TOP VIEW)  
Organization . . . 524288 By 8 Bits  
262144 By 16 Bits  
Array-Blocking Architecture  
V
1
2
3
4
5
6
7
8
9
44 RP  
43  
42 A8  
PP  
DU/WP  
A17  
A7  
W
– One 16K-Byte Protected Boot Block  
– Two 8K-Byte Parameter Blocks  
– One 96K-Byte Main Block  
– Three 128K-Byte Main Blocks  
– Top or Bottom Boot Locations  
41 A9  
A6  
A5  
A4  
A3  
A2  
A1 10  
A0 11  
40 A10  
39 A11  
38 A12  
37 A13  
36 A14  
35 A15  
’28F400Axy Offers a User-Defined 8-Bit  
(Byte) or 16-Bit (Word) Organization  
’28F004Axy Offers Only the 8-Bit  
Organization  
34  
33 BYTE  
32  
A16  
E
12  
13  
14  
Maximum Access/Minimum Cycle Time  
– Commercial and Extended  
V
V
SS  
SS  
G
31 DQ15/A  
30 DQ7  
29 DQ14  
–1  
DQ0 15  
DQ8 16  
DQ1 17  
DQ9 18  
DQ2 19  
DQ10 20  
DQ3 21  
DQ11 22  
5-V V  
± 10%  
3.3-V V  
± 0.3 V  
CC  
CC  
’28F400Axy60 60 ns 110 ns  
’28F400Axy70 70 ns 130ns  
’28F400Axy80 80 ns 150 ns  
28  
DQ6  
27 DQ13  
26 DQ5  
25 DQ12  
24 DQ4  
– Automotive (offered for only 5-V V  
voltage configurations)  
CC  
23  
V
CC  
5-V V  
± 10%  
CC  
’28F400Axy70 70 ns  
’28F400Axy80 80 ns  
’28F400Axy90 90 ns  
PIN NOMENCLATURE  
A0–A17  
BYTE  
Address Inputs  
Byte Enable  
(x = S, E, F, M, or Z Depending on V /V  
Configuration)  
(y = T or B for Top or Bottom Boot-Block  
Configuration)  
CC PP  
DQ0–DQ14 Data In/Out  
DQ15/A  
Data In/Out (word-wide mode),  
–1  
Low-Order Address (byte-wide mode)  
Chip Enable  
E
G
Output Enable  
100000 and 10000 Program/Erase Cycle  
Versions  
NC  
RP  
No Internal Connection  
Reset/Deep Power-Down  
Power Supply  
Three Temperature Ranges  
V
CC  
V
PP  
V
SS  
– Commercial . . . 0°C to 70°C  
– Extended . . . – 40°C to 85°C  
– Automotive . . . – 40°C to 125°C  
Power Supply for Program/Erase  
Ground  
W
Write Enable  
Industry Standard Packages Offered in  
– 40-Pin TSOP (DCD Suffix)  
– 44-Pin PSOP (DBJ Suffix)  
DU/WP  
Do Not Use for ’AMy or ’AZy /Write Protect  
Fully Automated On-Chip Erase and  
Word/Byte Program Operations  
– 48-Pin TSOP (DCD Suffix)  
Low Power Dissipation (V  
= 5.5 V)  
CC  
Write Protection for Boot Block  
– Active Write . . . 248 mW (Byte Write)  
– Active Read . . . 330 mW (Byte Read)  
– Active Write . . . 248 mW (Word Write)  
– Active Read . . . 330 mW (Word Read)  
– Block Erase . . . 165 mW  
Industry Standard Command-State Machine  
(CSM)  
– Erase Suspend/Resume  
– Algorithm-Selection Identifier  
Three Different Combinations of Supply  
Voltages Offered  
– Standby . . . 0.72 mW (CMOS-Input  
Levels)  
All Inputs/Outputs TTL Compatible  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...80

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