TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
DBJ PACKAGE
(TOP VIEW)
Organization . . . 262144 by 8 bits
131072 by 16 bits
Array-Blocking Architecture
– Two 8K-Byte Parameter Blocks
– One 96K-Byte Main Block
– One 128K-Byte Main Block
– One 16K-Byte Protected Boot Block
– Top or Bottom Boot Locations
V
1
2
3
4
5
6
7
8
9
44 RP
PP
NC
NC
A7
A6
A5
A4
A3
A2
43
W
42
A8
41 A9
40 A10
39 A11
38 A12
All Inputs/Outputs TTL Compatible
37
A13
36 A14
Maximum Access/Minimum Cycle Time
35
34
33
32
A1 10
A0 11
A15
A16
BYTE
V
± 10%
CC
’28F200BZx70
’28F200BZx80
’28F200BZx90
70 ns
80 ns
90 ns
E
12
13
14
V
V
SS
G
SS
31 DQ15/A
30 DQ7
29 DQ14
28 DQ6
–1
(x = top (T) or bottom (B) boot-block
configurations ordered)
DQ0 15
DQ8 16
DQ1 17
DQ9 18
DQ2 19
DQ10 20
DQ3 21
DQ11 22
10000 Program/Erase-Cycles
27
DQ13
Three Temperature Ranges
26 DQ5
25 DQ12
24 DQ4
– Commercial . . . 0°C to 70°C
– Extended . . . – 40°C to 85°C
– Automotive . . . – 40°C to 125°C
23
V
CC
Low Power Dissipation (V
= 5.5 V)
CC
– Active Write . . . 330 mW (Byte-Write)
– Active Read . . . 330 mW (Byte-Read)
– Active Write . . . 358 mW (Word-Write)
– Active Read . . . 330 mW (Word-Read)
– Block-Erase . . . 165 mW
– Standby . . . 0.55 mW (CMOS-Input
Levels)
– Deep Power-Down Mode . . . 0.0066 mW
PIN NOMENCLATURE
A0–A16
BYTE
Address Inputs
Byte Enable
DQ0–DQ14 Data In/Out
DQ15/A
Data In/Out (word-wide mode),
Low-Order Address (byte-wide mode)
Chip Enable
–1
E
G
Output Enable
NC
RP
No Internal Connection
Reset/Deep Power-Down
5-V Power Supply
12-V Power Supply for Program/Erase
Ground
Fully Automated On-Chip Erase and
Word/Byte-Program Operations
V
CC
V
PP
V
SS
Write-Protection for Boot Block
Industry-Standard Command State Machine
(CSM)
W
Write Enable
– Erase-Suspend/Resume
– Algorithm-Selection Identifier
description
The TMS28F200BZx is a 262144 by 8-bit/131072 by 16-bit (2097152-bit), boot-block flash memory that can
be electrically block-erased and reprogrammed. The TMS28F200BZx is organized in a blocked architecture
consisting of one 16K-byte protected boot block, two 8K-byte parameter blocks, one 96K-byte main block, and
one 128K-byte main block. The device can be ordered with either a top or bottom boot-block configuration.
Operation as a 256K-by 8-bit or a 128K-by16-bit organization is user-definable.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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