Datasheet > TMPM4KLFYAFG

TMPM4KLFYAFG

更新时间： 2024-11-21 14:57:39

品牌	Logo	应用领域
东芝 - TOSHIBA		/
页数	文件大小	规格书
101页	1621K
描述

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中文翻译

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数据手册

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TMPM4KLFYAFG 数据手册

TXZ+ Family

TMPM4K Group(2)

Datasheet

CMOS Digital Integrated Circuit Silicon Monolithic

TMPM4K Group(2)

General Description

LQFP100 14x14mm, 0.5mm pitch

LQFP80

LQFP64

12x12mm, 0.5mm pitch

14x14mm, 0.8mm pitch

10x10mm, 0.5mm pitch

●

Arm^®Cortex^®-M4 processor with FPU

Operating frequency: 1 to 160 MHz, Operating voltage: 2.7 to 5.5 V

QFP100

14x20mm, 0.65mm pitch

●

Code flash: 128 to 256 KB, Data flash: 32KB

Package: 64-pin to 100-pin. 6 types of packages are available.

Hardware IPs such as A-VE+, 12-bit ADC, and A-PMD are provided for implementation of vector control and PFC control

Applications

Motors, major appliances using motors, and industrial equipment.

Features

● Arm Cortex-M4 processor with FPU

‒ Operating frequency: 1 to 160 MHz

‒ Memory Protection Unit (MPU)

● Low-power consumption mode

‒ Operating voltage: 2.7 to 5.5 V

● On-chip debug (JTAG/SW), NBDIF(RAM monitor)

● Trigger Selector (TRGSEL)

‒ Expand Trigger request for DMAC, Timer, others

● DMA controller (DMAC): 1 unit

‒ DMA requests: 30 to 32 factors, internal/external triggers

● CRC Calculation Circuit (CRC): CRC32, CRC16

● Asynchronous Serial Interface (UART): 3 to 4 channels

‒ 5Mbps(Max), FIFO(Transmission 8-stage, Reception 8-stage)

● Serial Peripheral Interface (TSPI): 2 channels

4.5 to 5.5 V (All Functions)

2.7 to 4.5 V (Without OPAMP, ADC)

‒ Low-power consumption operation: IDLE, STOP1

● Operating temperature: -40 to +105°C

● Internal memory

‒ SIO/SPI mode, 10MHz(MAX), FIFO(Transmitter: 16bitx8,

Receive: 16bitx8)

‒ Code flash: 128 to 256 KB, rewritable up to 100,000 times

‒ Data flash: 32KB rewritable up to 100,000 times

‒ Data flash is rewritable in parallel with instruction execution

‒ RAM: 24KB, with parity

● I²C Interface

‒ I²C Interface (I2C): 2 channels, Multi Master

‒ I²C Interface Version A (EI2C): 2 channels

Multi Master, support 10bit Slave addressing

● 12-bit Analog to Digital Converter (ADC): 14 to 22 inputs in 3 units

‒ Conversion time: 0.91 µs (Fastest)

‒ Self-diagnosis support function

● Clock

‒ External high speed oscillator: 6 to 12 MHz(Ceramic, Crystal)

‒ External high speed clock input: 6 to 10 MHz

‒ Internal high speed oscillator (IHOSC1): 10 MHz, user

trimming function

● Operational Amplifier (OPAMP): 3 units

‒ Gain selectable

‒ PLL: 160 MHz output(System clock)

● Oscillation frequency detection (OFD): Abnormal system clock

detection

● Advanced programmable motor control circuit (A-PMD): 3

channels

● Voltage Detection (LVD): 8 level, Generate interrupts and reset

outputs

‒ 3-phase complementary PWM output, Synchronized with ADC

‒ PFC control: support 3-phase interleaved PFC

● Interruption

‒ Emergency stop function by external inputs (EMG pin, OVV pin)

‒ External factors: 15 to 20

(External pinsfactors: 20 to 32 pins, with DNF)

‒ Internal factors: 93 to 100

● I/O ports: 51 to 87 (Input:2, Output:1)

‒ 5V-tolerant, open-drain, pull-up/-down

Start of commercial production

2021-04

Toshiba Electronic Devices & Storage Corporation

2023-06-06

Rev.1.8

1 / 101

12 3 4 5 6 7...101

中文翻译

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