Datasheet > TMPM4GRFDFG

TMPM4GRFDFG

更新时间： 2024-11-10 14:57:23

品牌	Logo	应用领域
东芝 - TOSHIBA		/
页数	文件大小	规格书
144页	2545K
描述

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中文翻译

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数据手册

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TMPM4GRFDFG 数据手册

TXZ+ Family

TMPM4G Group (1)

Datasheet

CMOS Digital Integrated Circuit Silicon Monolithic

TXZ+ Family

LQFP176(20x20mm, 0.4mm pitch)

LQFP144(20x20mm, 0.5mm pitch)

LQFP100(14x14mm, 0.5mm pitch)

TMPM4G Group (1)

General Description

VFBGA177(13x13mm, 0.8mm pitch)

VFBGA145(12x12mm, 0.8mm pitch)

●

Arm^®Cortex^®-M4 (with FPU)

Operating frequency: 1 to 200 MHz, Operating voltage: 2.7 to 3.6 V

Code Flash: 512 KB to 2048 KB, Data Flash: 32KB

Built-in high speed 12-bit AD converter and plenty of timers/serial channels

Applications

TXZ+ family TMPM4G group(1) integrates widely used for the equipment in which high speed data procedure is required, such as

OA/digital products, industrial equipment, and others.

Features

● Arm Cortex-M4(with FPU)

● Interrupt

Operating frequency: 1 to 200 MHz

Memory Protection Unit (MPU)

External factors: 12 to 16

(External pins: 17 to 32 pins , with DNF)

Internal factors: 109 to 145

● Supply voltage and power consumption

● I/O ports: 91 to 155 (Input: 4, Output: 1)

Operating voltage: 2.7 to 3.6 V

Enable to select Pull-up/Pull-down resistor, Open-drain

5V tolerant, 3V tolerant

Low-power consumption operation: IDLE, STOP1, and STOP2

● Operating temperature:

- 40 to +85°C @ operating frequency 1 to 200 MHz

● Internal memory

● On-chip debug (JTAG/SW) and NBDIF (RAM monitor)

● Trigger selector (TRGSEL)

Expand trigger requests for DMA Controller, Timer counter, and

others.

Code Flash: 512 KB to 2048 KB, rewritable up to 100,000 times

Data Flash: 32 KB, rewritable up to 100,000 times

● DMA controller: 3 units

Data Flash is rewritable during instruction execution

RAM: 192 KB to 256 KB and Backup RAM: 2 KB (all products)

MDMAC: 1 unit, DMA requests: 30 to 32 factors,

internal/external triggers

● Clock

HDMAC: 2 units, DMA requests: 13 to 15 factors,

internal/external triggers

External high speed oscillator: 8 MHz to 20 MHz (Ceramic and

Crystal)

● External bus interface (EBIF)

External high speed clock input: 8 to 24 MHz

Expandable to 64MB (Program/data)

Internal high speed oscillator1 (IHOSC1):10 MHz, user trimming

function

External data bus (separate bus/multiplexed bus): 8/16 bit width

Chip select controller: 4 channels

Internal high speed oscillator2 (IHOSC2):10 MHz

PLL: 200 MHz output

● Asynchronous serial communication

UART: 3 to 6 channels, up tp 5.0 Mbps, FIFO (Transmission

stages and Reception 8 stages)

External low speed oscillator: 32.768 kHz

● Oscillation frequency detector (OFD): Abnormal system clock

FUART: 1 or 2 channels, up to 2.5 Mbps. FIFO (Transmission 32

stages and Reception 32 stages) and IrDA up to 115.2Kbps.

detection

● Voltage detection (LVD): 7 levels. selection between interrupts

and reset outputs

Start of commercial production

2021-07

2023-10-31

Rev.1.4

1 / 144

Toshiba Electronic Devices & Storage Corporation

12 3 4 5 6 7...144

中文翻译

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