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TMC2111AR3C PDF预览

TMC2111AR3C

更新时间: 2024-11-09 22:42:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD DSP外围设备移位寄存器微控制器和处理器外围集成电路
页数 文件大小 规格书
12页 72K
描述
Variable-Length Shift Register

TMC2111AR3C 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCJ,
针数:28Reach Compliance Code:compliant
ECCN代码:3A991.A.2HTS代码:8542.39.00.01
风险等级:5.58Is Samacsys:N
边界扫描:NO最大时钟频率:30 MHz
外部数据总线宽度:8JESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.505 mm
低功率模式:NO端子数量:28
最高工作温度:70 °C最低工作温度:
输出数据总线宽度:8封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:4.57 mm
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:11.505 mm
uPs/uCs/外围集成电路类型:DSP PERIPHERAL, PIPELINE REGISTERBase Number Matches:1

TMC2111AR3C 数据手册

 浏览型号TMC2111AR3C的Datasheet PDF文件第2页浏览型号TMC2111AR3C的Datasheet PDF文件第3页浏览型号TMC2111AR3C的Datasheet PDF文件第4页浏览型号TMC2111AR3C的Datasheet PDF文件第5页浏览型号TMC2111AR3C的Datasheet PDF文件第6页浏览型号TMC2111AR3C的Datasheet PDF文件第7页 
www.fairchildsemi.com  
TMC2 0 1 1 A/2 1 1 1 A  
Va ria b le -Le n g t h S h ift Re g is t e r  
Features  
Applications  
• Low power CMOS  
• Video filtering  
• TMC2011A is a pin compatible replacement for the  
TDC1011 and TMC2011  
• TMC2211A is a pin compatible replacement for the  
TMC2111  
• Inputs and outputs are TTL compatible  
• DC–40MHz clock rate  
• High speed data registers  
• Local storage registers  
• Digital delay lines  
• Television special effects  
• Pipeline register  
• Selectable delay lengths (TMC2011A: 3 to 18 stages,  
TMC2111A: 1 to 16 stages)  
• Special 4-bit wide mixed-delay mode (TMC2011A)  
• Available in 24-pin CERDIP and plastic DIP and 28-lead  
Plastic Leadless Chip Carrier  
Description  
The TMC2011A and TMC2111A are high-speed, byte-wide  
shift registers with programmable delay lengths.  
The TMC2011A and TMC2111A are fully synchronous,  
with all operations controlled by a single master clock. Input  
and output registers are positive-edge triggered D-type flip-  
flops. The length and mode controls are also registered. Both  
devices operate with a maximum clock rate of 40 MHz.  
The TMC2011A can be programmed to any length between  
3 and 18 stages. It offers a special split-word mode which  
allows for mixed delay lengths. The TMC2011A, con-  
structed in low-power CMOS, is pin and function compatible  
with the bipolar TDC1011.  
Fabricated in a submicron CMOS process, the TMC2011A  
and TMC2111A are TTL-compatible, and are available in  
24-pin CERDIP and Plastic DIP packages as well as a  
28-lead Plastic Leadless Chip Carrier.  
The TMC2111A is a byte-wide shift register that can be pro-  
grammed to lengths of 1 to 16 stages.  
Block Diagrams  
TMC2011A  
TMC2111A  
R
R
R
DI  
R
R
R
R
R
DI  
7-0  
1
14  
15  
3-0  
1
2
3
16  
17  
8
4
8
8
4
4
8
8
4
4
8-Bit Wide  
1 of 16 Selector  
4-Bit Wide  
1 of 16 Selector  
L
R
R
R
R
L
3-0  
DO  
3-0  
DO  
DO  
L
16  
L
18  
7-0  
3-0  
7-4  
4
8
8
8
4
4
4
4
4
4
4
65-2011A-02  
CLK  
4-Bit Wide  
1 of 16 Selector  
R
4
4
R
I
18  
MC  
4
4
CLK  
4
4
4
DI  
R
R
R
R
R
17  
7-4  
1
2
3
16  
65-2011A-01  
4
Rev. 1.1.0  

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