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TLP705 PDF预览

TLP705

更新时间: 2024-11-18 03:59:23
品牌 Logo 应用领域
东芝 - TOSHIBA 栅极光电输出元件双极性晶体管栅极驱动
页数 文件大小 规格书
6页 146K
描述
Plasma Display Panel. Industrial Inverter IGBT/Power MOS FET Gate Drive

TLP705 技术参数

生命周期:End Of Life包装说明:SDIP-6
Reach Compliance Code:unknownHTS代码:8541.40.80.00
风险等级:5.65Is Samacsys:N
其他特性:UL RECOGNIZED配置:SINGLE
最大正向电流:0.02 A最大绝缘电压:5000 V
安装特点:SURFACE MOUNT元件数量:1
最高工作温度:100 °C最低工作温度:-40 °C
光电设备类型:LOGIC IC OUTPUT OPTOCOUPLER标称响应时间:2e-7 ns
子类别:Optocoupler - IC Outputs最小供电电压:10 V
标称供电电压:20 V表面贴装:YES
Base Number Matches:1

TLP705 数据手册

 浏览型号TLP705的Datasheet PDF文件第2页浏览型号TLP705的Datasheet PDF文件第3页浏览型号TLP705的Datasheet PDF文件第4页浏览型号TLP705的Datasheet PDF文件第5页浏览型号TLP705的Datasheet PDF文件第6页 
TLP705  
TOSHIBA Photocoupler GaAAs IRED + Photo IC  
Preliminary  
TLP705  
Unit in mm  
Plasma Display Panel.  
Industrial Inverter  
4.58±0.25  
6
5
4
IGBT/Power MOS FET Gate Drive  
The TOSHIBA TLP705 consists of a GaAAs light emitting diode and a  
integrated photodetector.  
This unit is 6-lead SDIP package. TLP705 is 50% smaller than 8PIN DIP  
and has suited the safety standard reinforced insulation class.  
So mounting area in safety standard required equipment can be reduced.  
TLP705 is suitable for gate driving circuit of IGBT or power MOS FET.  
Especially TLP705 is capable of “direct” gate drive of lowr Power IGBTs.  
1
2
3
7.62±0.25  
1.27±0.2  
0.4±0.1  
1.25±0.25  
Peak output current  
Operating frequency  
Guaranteed performance over temperature : 40 to 100°C  
Supply current  
Power supply voltage  
Threshold input current  
: ±0.45 A (max)  
: 250kHz (max)  
10.0max  
11-5J1  
: 3mA (max)  
: 10 to 20 V  
TOSHIBA  
11-5J1  
Weight0.26 g (typ.)  
: I  
= 8 mA (max)  
FLH  
Switching time (t  
/ t  
)
: 200 ns (max)  
: 10 kV/µs  
: 5000 Vrms  
pLH pHL  
Common mode transient immunity  
Isolation voltage  
UL Recognized  
:UL1577, File No.E67349  
Construction Mechanical Rating  
7.62 mm pich  
standard type  
10.16 mm pich  
TLPXXXF type  
Creepage Distance  
Clearance  
7.0 mm (Min)  
7.0 mm (Min)  
0.4 mm (Min)  
8.0 mm (Min)  
8.0 mm (Min)  
0.4 mm (Min)  
Insulation Thickness  
Truth Table  
Input  
LED  
Tr1  
Tr2  
Output  
H
L
ON  
ON  
OFF  
ON  
H
L
OFF  
OFF  
Pin Configuration (top view)  
Schematic  
I
CC  
6
V
CC  
O
(Tr1)  
(Tr2)  
I
F
1: Anode  
1
2
3
6
5
4
1+  
2: NC  
I
3: Cathode  
4: GND  
V
O
F
5
3−  
V
5: V (output)  
O
4
6: V  
CC  
SHIELD  
GND  
SHIELD  
A 0.1 µF bypass capacitor must be connected  
between pin 6 and 4. (See Note 6)  
1
2004-10-19  

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