5秒后页面跳转
TLK1002A PDF预览

TLK1002A

更新时间: 2024-11-06 03:27:23
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
16页 618K
描述
DUAL SIGNAL CONDITIONING TRANSCEIVER

TLK1002A 数据手册

 浏览型号TLK1002A的Datasheet PDF文件第2页浏览型号TLK1002A的Datasheet PDF文件第3页浏览型号TLK1002A的Datasheet PDF文件第4页浏览型号TLK1002A的Datasheet PDF文件第5页浏览型号TLK1002A的Datasheet PDF文件第6页浏览型号TLK1002A的Datasheet PDF文件第7页 
TLK1002A  
DUAL SIGNAL CONDITIONING TRANSCEIVER  
www.ti.com  
SLLS661JUNE 2005  
FEATURES  
No External Filter Components Required for  
PLLs  
Fully Integrated Signal Conditioning  
Transceiver  
Supports Loop-Back Modes  
1.0–1.3 Gbps Operation  
Temperature Rating 0°C to 70°C  
Low Power CMOS Design (<300 mW)  
Small Footprint 4 mm × 4 mm 24-Lead QFN  
Package  
High Differential Output Voltage Swing  
(1600 mVp-p typical)  
APPLICATIONS  
400 mVp-p Differential Input Sensitivity  
High Input Jitter Tolerance 0.606 UI  
Single 1.8 V Power Supply  
Resynchronization in Both Directions for  
1.25 Gbps Links  
Repeater for 1.0625 Gbps Applications  
2.5 V Tolerant Control Inputs  
Differential VML Transmit Outputs With No  
External Components Necessary  
DESCRIPTION  
TLK1002A is a single-chip dual signal conditioning transceiver.  
This chip supports data rates from 1.0 Gbps up to 1.3 Gbps. An on-chip clock generation phase-locked loop  
(PLL) generates the required half-rate clock from an externally applied reference clock. This reference clock  
equals approximately one tenth of the data rate. It may be off frequency from both received data streams by up  
to ±200 ppm.  
Both data paths are implemented identical. The implemented input buffers provide an input sensitivity of 400  
mVp-p differential.  
The data paths tolerate up to 0.606 UI total input jitter. Signal retiming is performed by means of phase-locked  
loop (PLL) circuits. The retimed output signals are fed to VML output buffers, which provide output amplitudes of  
typical 1600mVp-p differential across the external 2x50 load.  
TLK1002A only requires a single 1.8 V supply voltage. Robust design avoids the necessity of special off-chip  
supply filtering.  
Advanced low power CMOS design leads to low power consumption.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

与TLK1002A相关器件

型号 品牌 获取价格 描述 数据表
TLK1002ARGER TI

获取价格

DUAL SIGNAL CONDITIONING TRANSCEIVER
TLK1002ARGERG4 TI

获取价格

DUAL SIGNAL CONDITIONING TRANSCEIVER
TLK1002ARGET TI

获取价格

DUAL SIGNAL CONDITIONING TRANSCEIVER
TLK1002ARGETG4 TI

获取价格

DUAL SIGNAL CONDITIONING TRANSCEIVER
TLK1002RGE TI

获取价格

暂无描述
TLK1002RGER TI

获取价格

IC TXRX SIGNAL COND DUAL 24-QFN
TLK10031 TI

获取价格

单通道 XAUI/10GBASE-KR 收发器
TLK10031CTR TI

获取价格

单通道 XAUI/10GBASE-KR 收发器 | CTR | 144 | -40 to
TLK10034 TI

获取价格

QUAD-CHANNEL XAUI/10GBASE-KR TRANSCEIVER
TLK10034_15 TI

获取价格

Quad-Channel XAUI/10GBASE-KR Transceiver