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TLK10021ZWQ PDF预览

TLK10021ZWQ

更新时间: 2024-11-06 12:15:51
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德州仪器 - TI 局域网
页数 文件大小 规格书
2页 658K
描述
10 Gbps PHY Transceiver for LAN/MAN/SAN Applications

TLK10021ZWQ 数据手册

 浏览型号TLK10021ZWQ的Datasheet PDF文件第2页 
R E A L W O R L D S I G N A L P R O C E S S I N G  
Product Bulletin  
TLK10021  
Key Features  
Minimal power consumption  
(800 mW)  
TLK10021—10 Gbps PHY Transceiver for  
LAN/MAN/SAN Applications  
• 1.2 V and 2.5 V power supplies  
On-chip clock generation and  
data recovery  
High-speed adaptive receive  
equalization  
power consumption (800 mW).  
The Texas Instruments (TI)  
Full PCS, PMA and XGXS  
sublayer functionality is provided  
TLK10021 device is a single channel  
monolithic CMOS physical layer  
• Multiple external reference clock  
frequencies  
• Optional 10 GHz / divide-by-64 output  
clock  
• Fast lock time – 30 ns  
• Programmable XAUI and XFI polarity  
• Programmable XAUI lane ordering  
• Adjustable XAUI transmit  
equalization  
• Multiple loopback modes  
• PRBS generator and checker  
• MDIO and SDA/SCL management  
interfaces  
through the consolidation of the  
(PHY) transceiver designed for use  
receiver and transmitter PHY  
in 10 Gbps applications. Its XFI-  
functions on a single chip, along  
compliant serial interconnect  
with the integration of encode/  
supports interfacing with XFP  
decode/alignment logic, FIFOs,  
modules at 10 Gigabit Ethernet  
integrated clock drivers, multiple  
or 10 Gigabit Fibre Channel data  
loopback features and PRBS  
rates. Its flexible system side  
generation, and verification for  
interconnect supports interfacing  
both the line side and the system  
with MACs and ASICs using a  
side. This combination reduces  
the number of components and  
XAUI interface.  
enables 10 Gbps Ethernet and  
Fibre Channel systems to  
dissipate much less power.  
The TLK10021 device makes use  
of CMOS technology to offer an  
advanced combination of high-  
• JTAG support  
• 13 x 13 mm PBGA package with  
1.0 mm ball pitch uses less board  
space  
performance (10 Gbps) and low-  
• 0.13 mm CMOS process  
Benefits  
• Enables increased port density  
• Dissipates very low power  
• Simplifies system clocking  
• Supports XFI-compliance  
• Supports different clocking rates  
• Helps meet clocking requirements  
• Handles bursty data  
Traffic or  
Queue  
Manager  
Packet or  
Network  
Processor  
MAC  
or  
ASIC  
XFP  
Module  
TLK10021  
XAUI-XFI  
XFI  
XAUI  
Figure 1: XFP-based Line Card  
• Eases board layout  
• Enhances data eye  
• Enhances testability  
• Uses standard control interface  
• Supports standard testing access  
• Lowers power consumption  
TLK 10021  
Line Side  
(Gbps)  
10.3125  
10.51875  
System Side  
Device  
10 Gigabit Ethernet  
10 Gigabit Fibre Channel  
(Gbps)  
4 x 3.125  
4 x 3.1875  
Standard  
IEEE802.3ae  
INCITS 10GFC  

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