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TLE2161MD

更新时间： 2024-11-23 08:44:59
品牌 Logo 应用领域
德州仪器 - TI 运算放大器输出元件输入元件驱动
页数 文件大小 规格书
29页 478K
描述
EXCALIBUR JFET-INPUT HIGH-OUTPUT-DRIVE mPOWER OPERATIONAL AMPLIFIERS

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TLE2161MD 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.33.00.01风险等级：5.73
放大器类型：OPERATIONAL AMPLIFIER架构：VOLTAGE-FEEDBACK
最大平均偏置电流 (IIB)：0.04 µA最小共模抑制比：65 dB
标称共模抑制比：65 dB频率补偿：YES (AVCL>=5)
最大输入失调电压：6000 µVJESD-30 代码：R-PDSO-G8
长度：4.9 mm低-偏置：YES
低-失调：NO微功率：YES
负供电电压上限：-19 V标称负供电电压 (Vsup)：-15 V
功能数量：1端子数量：8
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE电源：+-5/+-20 V
认证状态：Not Qualified座面最大高度：1.75 mm
最小摆率：5 V/us标称压摆率：10 V/us
子类别：Operational Amplifier最大压摆率：0.375 mA
供电电压上限：19 V标称供电电压 (Vsup)：15 V
表面贴装：YES技术：BIPOLAR
温度等级：MILITARY端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
标称均一增益带宽：5600 kHz最小电压增益：7000
宽度：3.9 mmBase Number Matches：1

TLE2161MD 数据手册

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TLE2161, TLE2161A, TLE2161B  
EXCALIBUR JFET-INPUT HIGH-OUTPUT-DRIVE  
µPOWER OPERATIONAL AMPLIFIERS  
SLOS049D – NOVEMBER 1989 – REVISED MAY 1996  
Excellent Output Drive Capability  
Wide Operating Supply Voltage Range  
V = ± 2.5 V Min at R = 100 Ω,  
V
= ± 3.5 V to ± 18 V  
O
L
CC ±  
V
= ± 5 V  
CC±  
High Open-Loop Gain . . . 280 V/mV Typ  
V
= ± 12.5 V Min at R = 600 Ω,  
O
L
Low Offset Voltage . . . 500 µV Max  
V
= ± 15 V  
CC±  
Low Offset Voltage Drift With Time  
Low Supply Current . . . 280 µA Typ  
0.04 µV/Month Typ  
Decompensated for High Slew Rate and  
Gain-Bandwidth Product  
Low Input Bias Current . . . 5 pA Typ  
A
= 0.5 Min  
VD  
Slew Rate = 10 V/µs Typ  
Gain-Bandwidth Product = 6.5 MHz Typ  
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE  
vs  
LOAD RESISTANCE  
description  
10  
8
The TLE2161, TLE2161A, and TLE2161B are  
JFET-input, low-power, precision operational  
amplifiers manufactured using the Texas  
Instruments Excalibur process. Decompensated  
for stability with a minimum closed-loop gain of 5,  
these devices combine outstanding output drive  
capability with low power consumption, excellent  
dc precision, and high gain-bandwidth product.  
V
T
A
= ± 5 V  
CC  
= 25°C  
±
6
In addition to maintaining the traditional JFET  
advantages of fast slew rates and low input bias  
and offset currents, the Excalibur process offers  
outstanding parametric stability over time and  
temperature. This results in a device that remains  
precise even with changes in temperature and  
over years of use.  
4
2
0
10  
100  
1 k  
10 k  
R
– Load Resistance – Ω  
L
AVAILABLE OPTIONS  
PACKAGE  
V
max  
IO  
SMALL  
OUTLINE  
(D)  
CHIP  
CARRIER  
(FK)  
CERAMIC  
DIP  
PLASTIC  
DIP  
T
A
AT 25°C  
(JG)  
(P)  
0°C  
to  
70°C  
500 µV  
1.5 mV  
3 mV  
—
—
—
TLE2161BCP  
TLE2161ACP  
TLE2161CP  
TLE2161ACD  
TLE2161CD  
—
—
—
—
–40°C  
to  
85°C  
500 µV  
1.5 mV  
3 mV  
—
TLE2161BIP  
TLE2161AIP  
TLE2161IP  
TLE2161AID  
TLE2161ID  
—
—
–55°C  
to  
125°C  
500 µV  
1.5 mV  
3 mV  
—
—
TLE2161BMJG  
TLE2161AMJG  
TLE2161MJG  
TLE2161BMP  
TLE2161AMP  
TLE2161MP  
TLE2161AMD  
TLE2161MD  
TLE2161AMFK  
TLE2161MFK  
The D packages are available taped and reeled. Add R suffix to device type (e.g., TLE2161ACDR).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...29

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