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TLC2933PWLE PDF预览

TLC2933PWLE

更新时间： 2024-11-29 22:26:07
品牌 Logo 应用领域
德州仪器 - TI 信号电路锁相环或频率合成电路光电二极管
页数 文件大小 规格书
21页 367K
描述
HIGH-PERFORMANCE PHASE-LOCKED LOOP

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中文翻译

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TLC2933PWLE 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：TSSOP, TSSOP14,.25
针数：14Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.17
其他特性：CAN ALSO OPERATE FROM A 4.75V TO 5.25V SUPPLY模拟集成电路 - 其他类型：PHASE LOCKED LOOP
JESD-30 代码：R-PDSO-G14长度：5 mm
功能数量：1端子数量：14
最高工作温度：75 °C最低工作温度：-20 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3/5 V认证状态：Not Qualified
座面最大高度：1.2 mm子类别：PLL or Frequency Synthesis Circuits
最大供电电压 (Vsup)：3.15 V最小供电电压 (Vsup)：2.85 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL EXTENDED
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

TLC2933PWLE 数据手册

 浏览型号TLC2933PWLE的Datasheet PDF文件第2页浏览型号TLC2933PWLE的Datasheet PDF文件第3页浏览型号TLC2933PWLE的Datasheet PDF文件第4页浏览型号TLC2933PWLE的Datasheet PDF文件第5页浏览型号TLC2933PWLE的Datasheet PDF文件第6页浏览型号TLC2933PWLE的Datasheet PDF文件第7页 
TLC2933  
HIGH-PERFORMANCE PHASE-LOCKED LOOP  
SLAS136A – APRIL 1996 – REVISED JUNE 1997  
†
Voltage-Controlled Oscillator (VCO)  
Section:  
PW PACKAGE  
(TOP VIEW)  
– Ring Oscillator Using Only One  
LOGIC V  
1
2
3
4
5
6
7
VCO V  
BIAS  
VCO IN  
VCO GND  
VCO INHIBIT  
PFD INHIBIT  
NC  
14  
13  
12  
11  
10  
9
DD  
DD  
External Bias Resistor (R  
– Lock Frequency:  
)
BIAS  
TEST  
VCO OUT  
FIN–A  
FIN–B  
PFD OUT  
LOGIC GND  
43 MHz to 100 MHz (V  
= 5 V ±5%,  
DD  
T = –20°C to 75°C, ×1 Output)  
A
37 MHz to 55 MHz (V  
= 3 V ±5%,  
DD  
T = –20°C to 75°C)  
A
8
Phase-Frequency Detector (PFD) Section  
Includes a High-Speed Edge-Triggered  
Detector With Internal Charge Pump  
†
Available in tape and reel only and ordered as the  
TLC2933PWLE.  
NC – No internal connection  
Independent VCO, PFD Power-Down Mode  
Thin Small-Outline Package (14 terminal)  
CMOS Technology  
Typical Applications:  
– Frequency Synthesis  
– Modulation/Demodulation  
– Fractional Frequency Division  
CMOS Input Logic Level  
description  
The TLC2933 is designed for phase-locked-loop (PLL) systems and is composed of a voltage-controlled  
oscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The oscillation frequency range  
of the VCO is set by an external bias resistor (R  
). The high-speed PFD with internal charge pump detects  
BIAS  
the phase difference between the reference frequency input and signal frequency input from the external  
counter. Both the VCO and the PFD have inhibit functions that can be used as a power-down mode. With the  
high-speed and stable VCO characteristics, the TLC2933 is well suited for use in high-performance PLL  
systems.  
functional block diagram  
12  
VCO IN  
4
5
9
13  
10  
2
Voltage-  
Controlled  
Oscillator  
Phase  
Frequency  
Detector  
FIN–A  
FIN–B  
BIAS  
VCO INHIBIT  
TEST  
3
6
VCO OUT  
PFD OUT  
PFD INHIBIT  
AVAILABLE OPTIONS  
PACKAGE  
T
A
SMALL OUTLINE  
(PW)  
–20°C to 75°C  
TLC2933PWLE  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...21

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