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TL16C554I

更新时间: 2024-11-21 22:42:11
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德州仪器 - TI 通信
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33页 477K
描述
ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C554I 数据手册

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TL16C554, TL16C554I  
ASYNCHRONOUS COMMUNICATIONS ELEMENT  
SLLS165D – JANUARY 1994 – REVISED JULY 1998  
Integrated Asynchronous Communications  
Element  
Fully Programmable Serial Interface  
Characteristics:  
– 5-, 6-, 7-, or 8-Bit Characters  
– Even-, Odd-, or No-Parity Bit  
– 1-, 1 1/2-, or 2-Stop Bit Generation  
– Baud Generation (DC to 1-Mbit Per  
Second)  
Consists of Four Improved TL16C550 ACEs  
Plus Steering Logic  
In FIFO Mode, Each ACE Transmitter and  
Receiver Is Buffered With 16-Byte FIFO to  
Reduce the Number of Interrupts to CPU  
False Start Bit Detection  
In TL16C450 Mode, Hold and Shift  
Registers Eliminate Need for Precise  
Synchronization Between the CPU and  
Serial Data  
Complete Status Reporting Capabilities  
Line Break Generation and Detection  
Internal Diagnostic Capabilities:  
– Loopback Controls for Communications  
Link Fault Isolation  
Up to 16-MHz Clock Rate for up to 1-Mbaud  
Operation  
– Break, Parity, Overrun, Framing Error  
Simulation  
Programmable Baud Rate Generators  
Which Allow Division of Any Input  
Reference Clock by 1 to (2 1) and  
16  
Fully Prioritized Interrupt System Controls  
Generate an Internal 16 × Clock  
Modem Control Functions (CTS, RTS, DSR,  
DTR, RI, and DCD)  
Adds or Deletes Standard Asynchronous  
Communication Bits (Start, Stop, and  
Parity) to or From the Serial Data Stream  
3-State Outputs Provide TTL Drive  
Capabilities for Bidirectional Data Bus and  
Control Bus  
Independently Controlled Transmit,  
Receive, Line Status, and Data Set  
Interrupts  
description  
The TL16C554 and the TL16C554I are enhanced quadruple versions of the TL16C550B asynchronous  
communications element (ACE). Each channel performs serial-to-parallel conversion on data characters  
received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted  
bytheCPU. ThecompletestatusofeachchannelofthequadrupleACEcanbereadatanytimeduringfunctional  
operation by the CPU. The information obtained includes the type and condition of the operation performed and  
any error conditions encountered.  
The TL16C554 and the TL16C554I quadruple ACE can be placed in an alternate FIFO mode, which activates  
the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in  
both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on  
the chip. Two terminal functions allow signaling of direct memory access (DMA) transfers. Each ACE includes  
a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and  
16  
(2 1).  
The TL16C554 and the TL16C554I are available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package and  
in an 80-pin (TQFP) PN package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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