TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
JT OR NT PACKAGE
(TOP VIEW)
•
•
58-MHz Max Clock Rate
Ideal for Waveform Generation and
High-Performance State Machine
Applications
CLK
I0
V
CC
I6
I7
I8
1
24
23
22
21
20
19
18
17
16
15
14
13
2
I1
I2
I3
I4
3
•
•
•
•
6-Bit Internal Binary Counter
8-Bit Internal State Register
Programmable Clock Polarity
4
I9
5
I10
I11
I12/OE
Q7
Q6
Q5
Q4
6
I5
7
Q0
Q1
Q2
Q3
GND
8
Outputs Programmable for Registered or
Combinational Operation
9
10
11
12
•
•
6-Bit Counter Simplifies Logic Equation
Development in State Machine Designs
Programmable Output Enable
FK OR FN PACKAGE
(TOP VIEW)
description
The TIBPSG507AC is
a 13 × 80 × 8
Programmable Sequence Generator (PSG) that
offers the system designer unprecedented
4
3
2
1
28 27 26
25
5
I2
I3
I4
NC
I5
Q0
Q1
I8
I9
I10
flexibility
in
a
high-performance
6
24
23
field-programmable logic device. Applications
such as waveform generators, state machines,
dividers, timers, and simple logic reduction are all
possible with the PSG. By utilizing the built-in
binary counter, the PSG is capable of generating
complex timing controllers. The binary counter
also simplifies logic equation development in state
machine and waveform generator applications.
7
8
22 NC
21 I11
20 I12/OE
19 Q7
9
10
11
12 13 14 15 16 17 18
The TIBPSG507AC contains 80 product (AND)
terms, a 6-bit binary counter with control logic,
eight S/R state holding registers, and eight
outputs. The eight outputs can be individually
NC – No internal connection
programmed
for
either
registered
or
combinational operation. The clock input is fuse
programmable for either positive- or negative-
edge operation.
The 6-bit binary counter is controlled by a synchronous-clear and a count/hold function. Each control function
has a nonregistered and registered option. When either SCLR0 or SCLR1 is taken high, the counter resets to
zero on the next active clock edge. When either CNT/HLD0 or CNT/HLD1 is taken high, the counter is held at
the present count and is not allowed to advance on the active clock edge. The SCLR function overrides the
CNT/HLD feature when both lines are simultaneously high.
Clock polarity is programmable through the clock polarity fuse. Leaving this fuse intact selects positive-edge
triggering. Negative-edge triggering is selected by blowing this fuse. Pin 17 functions as an input and/or an
output enable. When the output enable fuse is intact, all outputs are always enabled allowing pin 17 to be used
strictly as an input. Blowing the output enable fuse lets pin 17 function as an output enable and an input. In this
mode, the outputs are enabled when pin 17 is low and are in a high-impedance state when pin 17 is high.
PRODUCTION DATA information is current as of publication date.
Copyright 1995, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1