5秒后页面跳转
TIBPLS506AC PDF预览

TIBPLS506AC

更新时间: 2024-11-03 11:58:15
品牌 Logo 应用领域
德州仪器 - TI 可编程逻辑
页数 文件大小 规格书
16页 327K
描述
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER

TIBPLS506AC 数据手册

 浏览型号TIBPLS506AC的Datasheet PDF文件第2页浏览型号TIBPLS506AC的Datasheet PDF文件第3页浏览型号TIBPLS506AC的Datasheet PDF文件第4页浏览型号TIBPLS506AC的Datasheet PDF文件第5页浏览型号TIBPLS506AC的Datasheet PDF文件第6页浏览型号TIBPLS506AC的Datasheet PDF文件第7页 
TIBPLS506AC  
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER  
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995  
JT OR NT PACKAGE  
(TOP VIEW)  
58-MHz Max Clock Rate  
Two Transition Complement Array Terms  
16-Bit Internal State Registers  
8-Bit Output Registers  
CLK  
I0  
V
CC  
I6  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
2
I1  
I7  
3
I2  
I8  
4
Outputs Programmable for Registered or  
Combinational Operation  
I3  
I9  
5
I4  
I5  
I10  
I11  
I12/OE  
Q7  
Q6  
Q5  
Q4  
6
7
Ideal for Waveform Generation and  
High-Performance State Machine  
Applications  
Q0  
Q1  
Q2  
Q3  
GND  
8
9
10  
11  
12  
Programmable Output Enable  
Programmable Clock Polarity  
FK OR FN PACKAGE  
(TOP VIEW)  
description  
The TIBPLS506AC is a TTL field-programmable  
state machine of the Mealy type. This state  
machine (logic sequencer) contains 97 product  
terms (AND terms) and 48 sum terms (OR terms).  
The product and sum terms are used to control the  
16-bit internal state registers and the 8-bit output  
registers.  
4
3
2
1
28 27 26  
25  
5
I2  
I3  
I4  
NC  
I5  
Q0  
Q1  
I8  
I9  
I10  
6
24  
23  
7
8
22 NC  
21 I11  
20 I12/OE  
19 Q7  
9
The outputs of the internal state registers  
(P0P15) are fed back and combined with the
inputs (I0I12) to form the AND array. In addition,  
two sum terms are complemented and fed back to  
the AND array, which allows any product m to  
be summed, complemented, and used as inut to  
the AND array.  
10  
11  
12 13 14 15 16 17 18  
NC – No internal connection  
The eight output cells can be individually  
programmed for registered or combinational  
operation. Nonregistered operation is selected by  
blowing the output multiplexer fuse. Registered  
output operation is selected by leaving the output  
multiplexer fuse intact.  
Pin 17 can be programmeunction as an input and/or an output enable. Blowing the output enable fuse lets  
pin 17 function as an output enable but does not disconnect pin 17 from the input array. When the output enable  
fuse is intact, pin 17 functions only as an input with the outputs being permanently enabled.  
The state and output registers are synchronously clocked by the fuse programmable clock input. The clock  
polarity fuse selects either postive- or negative-edge triggering. Negative-edge triggering is selected by blowing  
the clock polarity e. Leaving this fuse intact selects positive-edge triggering. After power-up, the device must  
be initialized to the desired state. When the output multiplexer fuse is left intact, registered operation is selected.  
The TIBPLS506AC is characterized for operation from 0°C to 75°C.  
PRODUCTION DATA information is current as of publication date.  
Copyright 1995, Texas Instruments Incorporated  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
1

与TIBPLS506AC相关器件

型号 品牌 获取价格 描述 数据表
TIBPLS506ACFK TI

获取价格

OT PLD, 20ns, CQCC28
TIBPLS506ACFN TI

获取价格

13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUEN
TIBPLS506ACJT TI

获取价格

OT PLD, 20ns, CDIP24
TIBPLS506ACNT TI

获取价格

13 X 97 X 8 Field-Programmable Logic Sequencer 24-PDIP
TIBPLS506CFK TI

获取价格

OT PLD, 6ns, CQCC28
TIBPLS506CFN TI

获取价格

OT PLD, 6ns, PQCC28
TIBPLS506CJT TI

获取价格

OT PLD, 6ns, CDIP24
TIBPLS506CNT TI

获取价格

OT PLD, 6ns, PDIP24
TIBPLS506MFK TI

获取价格

OT PLD, 6ns, CQCC28
TIBPLS506MJT TI

获取价格

OT PLD, 6ns, CDIP24