5秒后页面跳转
捷配首页

Datasheet > 可编程逻辑 > 可编程逻辑器件> TIBPAL22VP10-25MJT
TIBPAL22VP10-25MJT PDF预览

TIBPAL22VP10-25MJT

更新时间： 2024-11-02 23:03:39
品牌 Logo 应用领域
德州仪器 - TI 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
17页 214K
描述
HIGH-PERFORMANCE IMPACT-X E PROGRAMMABLE ARRAY LOGIC CIRCUITS

阅读下载

中文翻译

获取价格

TIBPAL22VP10-25MJT 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：CERAMIC, DIP-24
针数：24Reach Compliance Code：not_compliant
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.92Is Samacsys：N
其他特性：PAL WITH MACROCELLS; 10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK架构：PAL-TYPE
最大时钟频率：25 MHzJESD-30 代码：R-GDIP-T24
专用输入次数：11I/O 线路数量：10
输入次数：22输出次数：10
产品条款数：120端子数量：24
最高工作温度：125 °C最低工作温度：-55 °C
组织：11 DEDICATED INPUTS, 10 I/O输出函数：MACROCELL
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP24,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V可编程逻辑类型：OT PLD
传播延迟：25 ns认证状态：Not Qualified
子类别：Programmable Logic Devices最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：NO技术：TTL
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

TIBPAL22VP10-25MJT 数据手册

 浏览型号TIBPAL22VP10-25MJT的Datasheet PDF文件第2页浏览型号TIBPAL22VP10-25MJT的Datasheet PDF文件第3页浏览型号TIBPAL22VP10-25MJT的Datasheet PDF文件第4页浏览型号TIBPAL22VP10-25MJT的Datasheet PDF文件第5页浏览型号TIBPAL22VP10-25MJT的Datasheet PDF文件第6页浏览型号TIBPAL22VP10-25MJT的Datasheet PDF文件第7页 
TIBPAL22VP10-20C, TIBPAL22VP10-25M  
PROGRAMMABLE ARRAY LOGIC CIRCUITS  
HIGH-PERFORMANCE IMPACT-X  
SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991  
C SUFFIX . . . NT PACKAGE  
M SUFFIX . . . JT PACKAGE  
•
Functionally Equivalent to the  
TIBPAL22V10/10A, with Additional  
Feedback Paths in the Output Logic  
Macrocell  
(TOP VIEW)  
CLK/I  
V
CC  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
I
I
I
I
I
I
I
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I
2
•
•
•
Choice of Operating Speeds:  
3
TIBPAL22VP10-20C . . . 20 ns Max  
TIBPAL22VP10-25M . . . 25 ns Max  
4
5
Variable Product Term Distribution  
Allows More Complex Functions to Be  
Implemented  
6
7
8
9
Each Output Is User Programmable for  
Registered or Combinational Operation,  
Polarity, and Output Enable Control  
I
I
10  
11  
12  
GND  
•
•
TTL-Level Preload for Improved Testability  
Extra Terms Provide Logical Synchronous  
Set and Asynchronous Reset Capability  
C SUFFIX . . . FN PACKAGE  
M SUFFIX . . . FK PACKAGE  
(TOP VIEW)  
•
Fast Programming, High Programming  
Yield, and Unsurpassed Reliability Ensured  
Using Ti-W Fuses  
•
•
•
AC and DC Testing Done at the Factory  
Utilizing Special Designed-In Test Features  
4
3
2
1
28 27 26  
25  
5
I
I
I
I/O/Q  
I/O/Q  
I/O/Q  
6
24  
23  
Dependable Texas Instruments Quality and  
Reliability  
7
8
NC  
22 NC  
9
I
I
I
Package Options Include Plastic  
Dual-In-Line and Chip Carrier Packages  
21 I/O/Q  
20 I/O/Q  
19 I/O/Q  
10  
11  
12 13 14 15 16 17 18  
description  
The TIBPAL22VP10’ is equivalent to the  
TIBPAL22V10A but offers additional flexibility in  
the output structure. The improved output  
macrocell uses the registered outputs as inputs  
when in a high-impedance condition. This  
provides two additional output configurations for a  
total of six possible macrocell configurations all of  
which are shown in Figure 1.  
NC – No internal connection  
Pin assignments in operating mode  
These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and  
programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered  
and inverting or noninverting. In addition, the data may be fed back into the array from either the register or the  
I/O port. The ten potential outputs are enabled through the use of individual product terms.  
Further advantages can be seen in the introduction of variable product term distribution. This technique  
allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This  
variable allocation of terms allows far more complex functions to be implemented than in previously available  
devices.  
These devices are covered by U.S. Patent 4,410,987.  
IMPACT-X is a trademark of Texas Instruments Incorporated.  
PRODUCTION DATA information is current as of publication date.  
Copyright 1991, Texas Instruments Incorporated  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Productionprocessingdoesnotnecessarilyinclude  
testing of all parameters.  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1
1234567...17

中文翻译

下载PDF

与TIBPAL22VP10-25MJT相关器件

型号 品牌 获取价格 描述 数据表
TIBPAL22VP10-25MJTB TI

获取价格

 		High-Performance Impact-X Programmable Array Logic Circuits 24-CDIP -55 to 125
TIBPAL22VP10-25MWB TI

获取价格

 		暂无描述
TIBPALR19L8CNT ROCHESTER

获取价格

 		OT PLD, 25ns, PDIP24
TIBPLS506AC TI

获取价格

 		13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUEN
TIBPLS506ACFK TI

获取价格

 		OT PLD, 20ns, CQCC28
TIBPLS506ACFN TI

获取价格

 		13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUEN
TIBPLS506ACJT TI

获取价格

 		OT PLD, 20ns, CDIP24
TIBPLS506ACNT TI

获取价格

 		13 X 97 X 8 Field-Programmable Logic Sequencer 24-PDIP
TIBPLS506CFK TI

获取价格

 		OT PLD, 6ns, CQCC28
TIBPLS506CFN TI

获取价格

 		OT PLD, 6ns, PQCC28

与TIBPAL22VP10-25MJT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证