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TIBPAL20R6-20MW PDF预览

TIBPAL20R6-20MW

更新时间： 2024-11-02 22:08:11
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
17页 185K
描述
HIGH-PERFORMANCE IMPACT E PAL CIRCUITS

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TIBPAL20R6-20MW 技术参数

生命周期：Obsolete包装说明：DFP,
Reach Compliance Code：unknownECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.69
其他特性：REGISTER PRELOAD; POWER-UP RESET最大时钟频率：28.5 MHz
JESD-30 代码：R-GDFP-F24专用输入次数：12
I/O 线路数量：2端子数量：24
最高工作温度：125 °C最低工作温度：-55 °C
组织：12 DEDICATED INPUTS, 2 I/O输出函数：MIXED
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
可编程逻辑类型：OT PLD传播延迟：25 ns
认证状态：Not Qualified最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：TTL
温度等级：MILITARY端子形式：FLAT
端子位置：DUALBase Number Matches：1

TIBPAL20R6-20MW 数据手册

 浏览型号TIBPAL20R6-20MW的Datasheet PDF文件第2页浏览型号TIBPAL20R6-20MW的Datasheet PDF文件第3页浏览型号TIBPAL20R6-20MW的Datasheet PDF文件第4页浏览型号TIBPAL20R6-20MW的Datasheet PDF文件第5页浏览型号TIBPAL20R6-20MW的Datasheet PDF文件第6页浏览型号TIBPAL20R6-20MW的Datasheet PDF文件第7页 
TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C  
TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M  
HIGH-PERFORMANCE IMPACT PAL CIRCUITS  
SRPS021 – D2920, JUNE 1986 – REVISED AUGUST 1989  
TIBPAL20L8’  
C SUFFIX . . . JT OR NT PACKAGE  
M SUFFIX . . . JT OR W PACKAGE  
•
High-Performance: f  
(w/o feedback)  
max  
TIBPAL20R’ -15C Series . . . 45 MHz  
TIBPAL20R’ -20M Series . . . 41.6 MHz  
(TOP VIEW)  
•
•
•
High-Performance . . . 45 MHz Min  
I
I
I
I
I
I
I
I
V
I
O
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
O
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
CC  
Reduced I  
of 180 mA Max  
CC  
2
3
Functionally Equivalent, but Faster Than  
PAL20L8, PAL20R4, PAL20R6, PAL20R8  
4
5
•
Power-Up Clear on Registered Devices (All  
Register Outputs are Set Low, but Voltage  
Levels at the Output Pins Go High)  
6
7
8
I
I
I
9
•
•
Preload Capability on Output Registers  
Simplifies Testing  
10  
11  
12  
I
I
Package Options Include Both Plastic and  
Ceramic Chip Carriers in Addition to Plastic  
and Ceramic DIPs  
GND  
TIBPAL20L8’  
C SUFFIX . . . FN PACKAGE  
M SUFFIX . . . FK PACKAGE  
I/O  
PORT  
S
I
3-STATE  
REGISTERED  
Q OUTPUTS  
DEVICE  
INPUTS O OUTPUTS  
(TOP VIEW)  
PAL20L8  
PAL20R4  
PAL20R6  
PAL20R8  
14  
12  
12  
12  
2
0
0
0
0
6
4
2
0
4 (3-state buffers)  
6 (3-state buffers)  
8 (3-state buffers)  
4
3
2
1
28 27 26  
25  
5
I
I
I
I/O  
I/O  
I/O  
description  
6
24  
23  
7
These programmable array logic devices feature  
high speed and functional equivalency when  
compared with currently available devices. These  
IMPACT circuits combine the latest Advanced  
Low-Power Schottky technology with proven  
titanium-tungsten fuses to provide reliable,  
high-performance substitutes for conventional  
TTL logic. Their easy programmability allows for  
quick design of custom functions and typically  
results in a more compact circuit board. In  
addition, chip carriers are available for futher  
reduction in board space.  
8
NC  
22 NC  
21 I/O  
20 I/O  
19 I/O  
9
I
I
I
10  
11  
12 13 14 15 16 17 18  
NC – No internal connection  
Pin assignments in operating mode  
Extra circuitry has been provided to allow loading of each register asynchronously to either a high or low state.  
This feature simplifies testing because the registers can be set to an initial state prior to executing the test  
sequence.  
The TIBPAL20’ C series is characterized from 0°C to 75°C. The TIBPAL20’ M series is characterized for  
operation over the full military temperature range of –55°C to 125°C.  
These devices are covered by U.S. Patent 4,410,987.  
IMPACT is a trademark of Texas Instruments Incorporated.  
PAL is a registered trademark of Advanced Micro Devices Inc.  
PRODUCTION DATA information is current as of publication date.  
Copyright 1989, Texas Instruments Incorporated  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily  
include testing of all parameters.  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1
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