TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Powerful 16-Bit TMS320C5x CPU
Multiple Phase-Locked Loop (PLL)
Clocking Options (×1, ×2, ×3, ×4, ×5, ×9
Depending on Device)
20-, 25-, 35-, and 50-ns Single-Cycle
Instruction Execution Time for 5-V
Operation
Block Moves for Data/Program
Management
25-, 40-, and 50-ns Single-Cycle Instruction
Execution Time for 3-V Operation
On-Chip Scan-Based Emulation Logic
Boundary Scan
Single-Cycle 16 × 16-Bit Multiply/Add
224K × 16-Bit Maximum Addressable
External Memory Space (64K Program, 64K
Data, 64K I/O, and 32K Global)
Five Packaging Options
– 100-Pin Quad Flat Package (PJ Suffix)
– 100-Pin Thin Quad Flat Package
(PZ Suffix)
– 128-Pin Thin Quad Flat Package
(PBK Suffix)
– 132-Pin Quad Flat Package (PQ Suffix)
– 144-Pin Thin Quad Flat Package
(PGE Suffix)
2K, 4K, 8K, 16K, 32K × 16-Bit Single-Access
On-Chip Program ROM
1K, 3K, 6K, 9K × 16-Bit Single-Access
On-Chip Program/Data RAM (SARAM)
1K Dual-Access On-Chip Program/Data
RAM (DARAM)
Low Power Dissipation and Power-Down
Modes:
– 47 mA (2.35 mA/MIP) at 5 V, 40-MHz
Clock (Average)
Full-Duplex Synchronous Serial Port for
Coder/Decoder Interface
Time-Division-Multiplexed (TDM) Serial Port
– 23 mA (1.15 mA/MIP) at 3 V, 40-MHz
Clock (Average)
– 10 mA at 5 V, 40-MHz Clock (IDLE1 Mode)
– 3 mA at 5 V, 40-MHz Clock (IDLE2 Mode)
– 5 µA at 5 V, Clocks Off (IDLE2 Mode)
Hardware or Software Wait-State
Generation Capability
On-Chip Timer for Control Operations
Repeat Instructions for Efficient Use of
Program Space
High-Performance Static CMOS Technology
Buffered Serial Port
Host Port Interface
†
IEEE Standard 1149.1 Test-Access Port
(JTAG)
description
The TMS320C5x generation of the Texas Instruments (TI ) TMS320 digital signal processors (DSPs) is
fabricated with static CMOS integrated circuit technology; the architectural design is based upon that of an
earlier TI DSP, the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals,
on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of
‡
the ’C5x devices. They execute up to 50 million instructions per second (MIPS).
The ’C5x devices offer these advantages:
Enhanced TMS320 architectural design for increased performance and versatility
Modular architectural design for fast development of spin-off devices
Advanced integrated-circuit processing technology for increased performance
Upward-compatible source code (source code for ’C1x and ’C2x DSPs is upward compatible with ’C5x DSPs.)
Enhanced TMS320 instruction set for faster algorithms and for optimized high-level language operation
New static-design techniques for minimizing power consumption and maximizing radiation tolerance
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI is a trademark of Texas Instruments Incorporated.
†
‡
IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture
References to ’C5x in this document include both TMS320C5x and TMS320LC5x devices unless specified otherwise.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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