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NE555DRG3 PDF预览

NE555DRG3

更新时间： 2024-01-27 23:41:43
品牌 Logo 应用领域
德州仪器 - TI 模拟波形发生功能信号电路光电二极管
页数 文件大小 规格书
29页 713K
描述
PRCISION TIMERS

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NE555DRG3 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOIC-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.65
Is Samacsys：N其他特性：CAN ALSO OPERATE FROM A 15V NOMINAL SUPPLY
模拟集成电路 - 其他类型：PULSE; RECTANGULARJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.9 mm
湿度敏感等级：1功能数量：1
端子数量：8最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：5/15 V
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：Analog Waveform Generation Functions最大供电电压 (Vsup)：16 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BIPOLAR
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9 mmBase Number Matches：1

NE555DRG3 数据手册

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NA555, NE555, SA555, SE555  
www.ti.com  
SLFS022H –SEPTEMBER 1973–REVISED JUNE 2010  
PRECISION TIMERS  
Check for Samples: NA555, NE555, SA555, SE555  
1
FEATURES  
•
Timing From Microseconds to Hours  
•
•
Adjustable Duty Cycle  
•
Astable or Monostable Operation  
TTL-Compatible Output Can Sink or Source up  
to 200 mA  
NA555...D OR P PACKAGE  
SE555...FK PACKAGE  
(TOP VIEW)  
NE555...D, P, PS, OR PW PACKAGE  
SA555...D OR P PACKAGE  
SE555...D, JG, OR P PACKAGE  
(TOP VIEW)  
3
2
1 20 19  
18  
1
2
3
4
GND  
TRIG  
OUT  
VCC  
8
7
6
5
NC  
NC  
4
5
6
7
8
DISCH  
THRES  
CONT  
DISCH  
NC  
THRES  
NC  
TRIG  
NC  
OUT  
NC  
17  
16  
15  
14  
RESET  
9 10 11 12 13  
NC – No internal connection  
DESCRIPTION/ORDERING INFORMATION  
These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the  
time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and  
capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled  
independently with two external resistors and a single external capacitor.  
The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be  
altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is  
set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the  
threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs  
and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes  
low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.  
The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of  
5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1973–2010, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
On products compliant to MIL-PRF-38535, all parameters are  
Instruments standard warranty. Production processing does not  
tested unless otherwise noted. On all other products, production  
necessarily include testing of all parameters.  
processing does not necessarily include testing of all parameters.  
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