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CD4541BM PDF预览

CD4541BM

更新时间: 2024-02-01 00:26:09
品牌 Logo 应用领域
德州仪器 - TI 计数器触发器逻辑集成电路光电二极管高压
页数 文件大小 规格书
9页 95K
描述
CMOS PROGRAMMABLE TIMER HIGH VOLTAGE TYPES(20V RATING)

CD4541BM 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.24计数方向:UP
系列:4000/14000/40000JESD-30 代码:R-PDSO-G14
长度:5 mm负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER工作模式:SYNCHRONOUS
位数:16功能数量:1
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):10.5 ns认证状态:Not Qualified
座面最大高度:1.2 mm标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:4.4 mm

CD4541BM 数据手册

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CD4541B  
CMOS Programmable Timer  
Data sheet acquired from Harris Semiconductor  
SCHS085  
High Voltage Types (20V Rating)  
Features  
Description  
• Low Symmetrical Output Resistance, Typically 100  
CD4541B programmable timer consists of a 16-stage binary  
counter, an oscillator that is controlled by external R-C compo-  
nents (2 resistors and a capacitor), an automatic power-on  
reset circuit, and output control logic. The counter increments  
on positive-edge clock transitions and can also be reset via the  
MASTER RESET input.  
at V  
= 15V  
DD  
[ /Title  
(CD45  
41B)  
/Sub-  
ject  
• Built-In Low-Power RC Oscillator  
• Oscillator Frequency Range . . . . . . . . . . DC to 100kHz  
• External Clock (Applied to Pin 3) can be Used Instead  
of Oscillator  
The output from this timer is the Q or Q output from the 8th,  
10th, 13th, or 16th counter stage. The desired stage is chosen  
using time-select inputs A and B (see Frequency Select Table).  
The output is available in either of two modes selectable via the  
MODE input, pin 10 (see Truth Table). When this MODE input is  
a logic “1”, the output will be a continuous square wave having  
N
• Operates as 2 Frequency Divider or as a Single-  
Transition Timer  
(CMO  
S Pro-  
gram-  
mable  
Timer  
High  
Volt-  
age  
Types  
(20V  
Rat-  
ing))  
/Autho  
r ()  
/Key-  
words  
(Har-  
ris  
Semi-  
con-  
ductor,  
CD400  
0,  
metal  
gate,  
• Q/Q Select Provides Output Logic Level Flexibility  
• AUTO or MASTER RESET Disables Oscillator During  
Reset to Reduce Power Dissipation  
N
a frequency equal to the oscillator frequency divided by 2 .  
• Operates With Very Slow Clock Rise and Fall Times  
With the MODE input set to logic “0” and after a MASTER  
• Capable of Driving Six Low Power TTL Loads, Three  
Low-Power Schottky Loads, or Six HTL Loads Over  
the Rated Temperature Range  
RESET is initiated, the output (assuming Q output has been  
N-1  
selected) changes from a low to a high state after 2  
counts  
and remains in that state until another MASTER RESET pulse  
is applied or the MODE input is set to a logic “1”.  
• Symmetrical Output Characteristics  
• 100% Tested for Quiescent Current at 20V  
• 5V, 10V, and 15V Parametric Ratings  
Timing is initialized by setting the AUTO RESET input (pin 5) to  
logic “0” and turning power on. If pin 5 is set to logic “1”, the  
AUTO RESET circuit is disabled and counting will not start until  
after a positive MASTER RESET pulse is applied and returns  
to a low level. The AUTO RESET consumes an appreciable  
amount of power and should not be used if low-power operation  
• Meets All Requirements of JEDEC Standard No. 13B,  
“Standard Specifications for Description of ‘B’ Series  
CMOS Devices”  
is desired. For reliable automatic power-on reset, V  
be greater than 5V.  
should  
DD  
Ordering Information  
TEMP.  
PKG.  
NO.  
The RC oscillator, shown in Figure 2, oscillates with a  
frequency determined by the RC network and is calculated  
using:  
o
PART NUMBER RANGE ( C)  
PACKAGE  
CD4541BF  
CD4541BE  
CD4541BH  
CD4541BM  
-55 to 125 14 Ld CERDIP  
-55 to 125 14 Ld PDIP  
-55 to 125 Chip  
F14.3  
E14.3  
-
Where f is between 1kHz  
and 100kHz  
1
----------------------------------  
f =  
2.3 R  
C
TC TC  
and R 10kand 2R  
S
TC  
-55 to 125 14 Ld SOIC  
M14.15  
Pinout  
CD4541B (CERDIP, PDIP, SOIC)  
TOP VIEW  
CMOS  
, pdip,  
cerdip,  
mil,  
mili-  
tary,  
R
C
1
2
3
4
5
6
7
14  
13  
12  
V
DD  
TC  
B
A
TC  
R
S
NC  
11 NC  
mil  
AUTO RESET  
10 MODE  
MASTER RESET  
9
8
Q/Q SELECT  
OUTPUT  
V
SS  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1378.1  
Copyright © Harris Corporation 1998  
1

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