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Datasheet > 驱动程序和接口 > 线路驱动器或接收器> 74LVCZ161284AGRG4
74LVCZ161284AGRG4 PDF预览

74LVCZ161284AGRG4

更新时间： 2024-02-03 17:55:50
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
13页 277K
描述
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP

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74LVCZ161284AGRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.53
差分输出：NO驱动器位数：14
输入特性：STANDARD接口集成电路类型：LINE TRANSCEIVER
接口标准：IEEE 1284JESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：12.5 mm
湿度敏感等级：1功能数量：13
端子数量：48最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：Not Qualified最大接收延迟：22 ns
接收器位数：13座面最大高度：1.2 mm
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：5.5 V
电源电压1-分钟：3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
最大传输延迟：22 ns宽度：6.1 mm
Base Number Matches：1

74LVCZ161284AGRG4 数据手册

 浏览型号74LVCZ161284AGRG4的Datasheet PDF文件第2页浏览型号74LVCZ161284AGRG4的Datasheet PDF文件第3页浏览型号74LVCZ161284AGRG4的Datasheet PDF文件第4页浏览型号74LVCZ161284AGRG4的Datasheet PDF文件第5页浏览型号74LVCZ161284AGRG4的Datasheet PDF文件第6页浏览型号74LVCZ161284AGRG4的Datasheet PDF文件第7页 
SN74LVCZ161284A  
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER  
WITH ERROR-FREE POWER UP  
www.ti.com  
SCES358B–SEPTEMBER 2001–REVISED MAY 2005  
FEATURES  
DGG PACKAGE  
(TOP VIEW)  
•
Power-On Reset (POR) Prevents Printer  
Errors When Printer Is Turned On, But No  
Valid Signal Is at Pins A9–A13  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
HD  
A9  
DIR  
Y9  
2
•
•
Operates From 3 V to 3.6 V  
3
A10  
A11  
A12  
A13  
Y10  
Y11  
Y12  
Y13  
1.4-kΩ Pullup Resistors Integrated on All  
Open-Drain Outputs Eliminate the Need for  
Discrete Resistors  
4
5
6
•
Designed for IEEE Std 1284-I (Level-1 Type)  
and IEEE Std 1284-II (Level-2 Type) Electrical  
Specifications  
7
V
V
CABLE  
CC  
CC  
8
A1  
A2  
B1  
B2  
9
•
•
•
•
Flow-Through Architecture Optimizes PCB  
Layout  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
GND  
A3  
A4  
GND  
B3  
B4  
Ioff and Power-Up 3-State Support Hot  
Insertion  
A5  
B5  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
A6  
GND  
A7  
B6  
GND  
B7  
B8  
V
ESD Protection Exceeds JESD 22  
– 4000-V Human-Body Model (A114-A)  
– 350-V Machine Model (A115-A)  
A8  
V
CABLE  
CC  
CC  
PERI LOGIC IN  
PERI LOGIC OUT  
C14  
C15  
C16  
– 1500-V Charged-Device Model (C101)  
A14  
A15  
A16  
A17  
DESCRIPTION/ORDERING INFORMATION  
C17  
The SN74LVCZ161284A is designed for 3-V to 3.6-V  
VCC operation. This device provides asynchronous  
two-way communication between data buses. The  
control-function implementation minimizes external  
timing requirements.  
HOST LOGIC OUT  
HOST LOGIC IN  
This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control (DIR) input  
is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side and  
four receivers. The SN74LVCZ161284A has one receiver dedicated to the HOST LOGIC line and a driver to  
drive the PERI LOGIC line.  
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a  
totem-pole configuration and in an open-drain configuration when HD is low. This meets the drive requirements  
as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface  
specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have  
a 1.4-kΩ integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low  
state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.  
The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs  
and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even  
when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
LVCZ161284A  
0°C to 70°C  
TSSOP – DGG  
Tape and reel  
SN74LVCZ161284AGR  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2001–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...13

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