5秒后页面跳转
捷配首页

Datasheet > 驱动程序和接口 > 线路驱动器或接收器> 74LVC161284DGGRG4
74LVC161284DGGRG4 PDF预览

74LVC161284DGGRG4

更新时间： 2024-01-19 15:53:31
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
12页 206K
描述
19-BIT BUS INTERFACE

阅读下载

获取价格

74LVC161284DGGRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：GREEN, PLASTIC, TSS0P-48针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：5.38Is Samacsys：N
其他特性：CONTAINS 5 DRIVERS, 4 RECEIVERS AND EIGHT BI-DIRECTIONAL LINES差分输出：NO
驱动器位数：8输入特性：SCHMITT TRIGGER
接口集成电路类型：LINE TRANSCEIVER接口标准：IEEE 1284
JESD-30 代码：R-PDSO-G48JESD-609代码：e4
长度：12.5 mm湿度敏感等级：1
位数：19功能数量：1
端子数量：48最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
最大输出低电流：0.084 A输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
最大接收延迟：40 ns接收器位数：8
座面最大高度：1.2 mm最大压摆率：45 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：5.5 V
电源电压1-分钟：3 V电源电压1-Nom：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
最大传输延迟：40 ns宽度：6.1 mm
Base Number Matches：1

74LVC161284DGGRG4 数据手册

 浏览型号74LVC161284DGGRG4的Datasheet PDF文件第2页浏览型号74LVC161284DGGRG4的Datasheet PDF文件第3页浏览型号74LVC161284DGGRG4的Datasheet PDF文件第4页浏览型号74LVC161284DGGRG4的Datasheet PDF文件第5页浏览型号74LVC161284DGGRG4的Datasheet PDF文件第6页浏览型号74LVC161284DGGRG4的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢇ ꢉꢊ ꢃ  
ꢇ ꢋ ꢌꢍꢎ ꢏ ꢍꢐꢀ ꢎꢁ ꢏꢑ ꢒꢓꢔ ꢆꢑ  
SCAS583J − NOVEMBER 1996 − REVISED FEBRUARY 2005  
DGG OR DL PACKAGE  
(TOP VIEW)  
D
D
D
1.4-kΩ Pullup Resistors Integrated on All  
Open-Drain Outputs Eliminate the Need for  
Discrete Resistors  
HD  
A9  
1
48 DIR  
47 Y9  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
2
A10  
A11  
A12  
A13  
3
46 Y10  
45 Y11  
4
Designed for the IEEE Std 1284-I (Level 1  
Type) and IEEE Std 1284-II (Level 2 Type)  
Electrical Specifications  
5
44  
Y12  
6
43 Y13  
7
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
V
V
CABLE  
CC  
CC  
A1  
D
D
Flow-Through Architecture Optimizes PCB  
Layout  
8
B1  
B2  
GND  
B3  
B4  
B5  
B6  
GND  
B7  
B8  
9
A2  
GND  
A3  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin-Shrink  
Small-Outline (DGG) Packages  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
A4  
A5  
A6  
description/ordering information  
GND  
A7  
The SN74LVC161284 is designed for 3-V to 3.6-V  
V
operation.  
This  
device  
provides  
CC  
A8  
asynchronous two-way communication between  
data buses. The control-function implementation  
minimizes external timing requirements.  
V
V
CABLE  
CC  
CC  
PERI LOGIC IN  
PERI LOGIC OUT  
C14  
C15  
C16  
A14  
A15  
A16  
A17  
This device has eight bidirectional bits; data can  
flow in the A-to-B direction when DIR is high and  
in the B-to-A direction when DIR is low. This  
device also has five drivers, which drive the cable  
side, and four receivers. The SN74LVC161284  
has one receiver dedicated to the HOST LOGIC  
line and a driver to drive the PERI LOGIC line.  
C17  
HOST LOGIC OUT  
HOST LOGIC IN  
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in  
a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive  
requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level 2 type) parallel  
peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have  
a 1.4-kΩ integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low  
state or if the output voltage is above V  
CABLE. If V  
CABLE is off, PERI LOGIC OUT is set to low.  
CC  
CC  
The device has two supply voltages. V  
is designed for 3-V to 3.6-V operation. V  
CABLE supplies the inputs  
CC  
CC  
and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even  
when V CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.  
CC  
The SN74LVC161284 is characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢕ
ꢕ
ꢒ
ꢖ
ꢧ
ꢗ
ꢢ
ꢐ
ꢆ
ꢠ
ꢏ
ꢡ
ꢎ
ꢛ
ꢖ
ꢙ
ꢁ
ꢚ
ꢗ
ꢔ
ꢏ
ꢔ
ꢘ
ꢙ
ꢣ
ꢚ
ꢛ
ꢡ
ꢜ
ꢝ
ꢞ
ꢞ
ꢟ
ꢟ
ꢘ
ꢘ
ꢛ
ꢛ
ꢙ
ꢙ
ꢘ
ꢠ
ꢠ
ꢤ
ꢡ
ꢢ
ꢜ
ꢜ
ꢣ
ꢣ
ꢙ
ꢟ
ꢞ
ꢝ
ꢠ
ꢠ
ꢛ
ꢚ
ꢤ
ꢏꢣ  
ꢢ
ꢥ
ꢠ
ꢦ
ꢘ
ꢡ
ꢞ
ꢠ
ꢟ
ꢘ
ꢟ
ꢛ
ꢜ
ꢙ
ꢢ
ꢧ
ꢞ
ꢙ
ꢟ
ꢟ
ꢣ
ꢠ
ꢨ
Copyright 2005 Texas Instruments Incorporated  
ꢜ
ꢛ
ꢡ
ꢟ
ꢛ
ꢜ
ꢝ
ꢟ
ꢛ
ꢠ
ꢤ
ꢘ
ꢚ
ꢘ
ꢡ
ꢣ
ꢜ
ꢟ
ꢩ
ꢟ
ꢣ
ꢜ
ꢛ
ꢚ
ꢪ
ꢞ
ꢎ
ꢙ
ꢝ
ꢣ
ꢠ
ꢟ
ꢞ
ꢙ
ꢧ
ꢞ
ꢜ
ꢧ
ꢫ
ꢞ
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢜ
ꢜ
ꢞ
ꢙ
ꢟ
ꢬ
ꢨ
ꢕ
ꢜ
ꢛ
ꢧ
ꢢ
ꢡ
ꢟ
ꢘ
ꢛ
ꢙ
ꢤ
ꢜ
ꢛ
ꢡ
ꢣ
ꢠ
ꢠ
ꢘ
ꢙ
ꢭ
ꢧ
ꢛ
ꢣ
ꢠ
ꢙ
ꢛ
ꢟ
ꢙ
ꢣ
ꢡ
ꢣ
ꢠ
ꢠ
ꢞ
ꢜ
ꢘ
ꢦ
ꢬ
ꢘ
ꢙ
ꢡ
ꢦ
ꢢ
ꢧ
ꢣ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

下载PDF

与74LVC161284DGGRG4相关器件

型号 品牌 描述 获取价格 数据表
74LVC161284DLRE4 TI 19-BIT BUS INTERFACE

获取价格
74LVC161284DLRG4 TI 19-BIT BUS INTERFACE

获取价格
74LVC161284PA IDT Bus Driver/Transceiver, 1-Func, 8-Bit, True Output, CMOS, PDSO48

获取价格
74LVC161284PV IDT Bus Driver/Transceiver, 1-Func, 8-Bit, True Output, CMOS, PDSO48

获取价格
74LVC161284TTR STMICROELECTRONICS LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER

获取价格
74LVC161BQ NEXPERIA Presettable synchronous 4-bit binary counter; asynchronous resetProduction

获取价格

与74LVC161284DGGRG4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证