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74ACT11191 PDF预览

74ACT11191

更新时间: 2024-02-10 10:57:07
品牌 Logo 应用领域
德州仪器 - TI 计数器
页数 文件大小 规格书
9页 135K
描述
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER

74ACT11191 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP20,.3Reach Compliance Code:unknown
风险等级:5.84计数方向:BIDIRECTIONAL
JESD-30 代码:R-PDIP-T20JESD-609代码:e0
负载电容(CL):50 pF负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:65000000 Hz
最大I(ol):0.024 A工作模式:SYNCHRONOUS
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5 V
认证状态:Not Qualified子类别:Counters
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

74ACT11191 数据手册

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ꢀ ꢁꢂ ꢃ ꢄꢅꢅꢅꢆ ꢅ  
ꢇꢈ ꢉꢃꢊꢋꢌ ꢉꢌ ꢍꢇ ꢎꢁ ꢏꢐꢑꢄ ꢎ ꢍꢒꢓꢔ ꢌꢕ ꢉꢎꢐꢑ ꢉꢂꢋꢈꢎꢃꢌ ꢍ ꢉꢄ ꢖꢋ  
SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993  
DW OR N PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Single Down/Up Count Control Line  
Look-Ahead Circuitry Enhances Speed of  
RCO  
D/U  
CLK  
A
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
Cascaded Counters  
Q
A
Fully Synchronous in Count Modes  
Q
B
Asynchronously Presettable With Load  
GND  
GND  
GND  
GND  
B
V
V
Control  
CC  
CC  
Flow-Through Architecture Optimizes  
C
PCB Layout  
Q
Q
D
CTEN  
LOAD  
C
D
Center-Pin V  
and GND Configurations to  
Minimize High-Speed Switching Noise  
CC  
MAX/MIN  
EPICt (Enhanced-Performance Implanted  
CMOS) 1-mm Process  
Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
description  
The 74ACT11191 is a synchronous, 4-bit binary reversible up/down counter. A synchronous counting operation  
is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other  
when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally  
associated with asynchronous (ripple clock) counters.  
The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock input if the enable  
input (CTEN) is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of  
the down/up (D/U) input. When D/U is low, the counter counts up and when D/U is high, it counts down.  
These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that  
will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function  
of the counter will be dictated solely by the condition meeting the stable setup and hold times.  
logic symbol  
CTRDIV16  
12  
20  
G1  
CTEN  
D/U  
10  
1
M2 [DOWN]  
M3 [UP]  
1,2−/1,3+  
G4  
2(CT=0)Z6  
3(CT=15)Z6  
MAX/MIN  
RCO  
19  
11  
CLK  
6,1,4  
LOAD  
C5  
2
3
8
9
18  
17  
14  
13  
A
B
5D  
[1]  
[2]  
[4]  
[8]  
Q
Q
Q
Q
A
B
C
D
C
D
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
EPIC is a trademark of Texas Instruments Incorporated.  
ꢄꢣ  
Copyright 1993, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  

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