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74AC11590N

更新时间： 2024-01-11 10:56:22
品牌 Logo 应用领域
德州仪器 - TI 计数器输出元件
页数 文件大小 规格书
9页 124K
描述
8-Bit Binary Counters With Registered 3-State Outputs 20-PDIP -40 to 85

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74AC11590N 技术参数

生命周期：Active包装说明：DIP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.78其他特性：TCO OUTPUT; REGISTERED OUTPUTS; CENTER VCC/GND PINS
计数方向：UP系列：AC
JESD-30 代码：R-PDIP-T20长度：24.325 mm
负载/预设输入：NO逻辑集成电路类型：BINARY COUNTER
工作模式：ASYNCHRONOUS位数：8
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：12.1 ns
座面最大高度：5.08 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：7.62 mm
最小 fmax：80 MHz

74AC11590N 数据手册

 浏览型号74AC11590N的Datasheet PDF文件第2页浏览型号74AC11590N的Datasheet PDF文件第3页浏览型号74AC11590N的Datasheet PDF文件第4页浏览型号74AC11590N的Datasheet PDF文件第5页浏览型号74AC11590N的Datasheet PDF文件第6页浏览型号74AC11590N的Datasheet PDF文件第7页 
74AC11590  
8-BIT BINARY COUNTER  
WITH REGISTERED 3-STATE OUTPUTS  
SCAS194 – D3988, MARCH 1992 – REVISED APRIL 1993  
DW OR N PACKAGE  
(TOP VIEW)  
• Parallel Registered Outputs  
• Internal Counters Have Direct Clear  
• Flow-Through Architecture Optimizes  
Q
Q
Q
GND  
GND  
GND  
GND  
Q
A
CCK  
CCKEN  
CCLR  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
B
PCB Layout  
C
D
• Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
V
CC  
• EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
V
CC  
OE  
RCK  
RCO  
• 500-mA Typical Latch-Up Immunity  
at 125°C  
Q
Q
F
E
• Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
Q
Q
H
G
description  
The 74AC11590 contains an 8-bit binary counter that feeds an 8-bit storage register. The storage register has  
parallel outputs. Separate clocks are provided for both the binary counter and storage register.  
The binary counter features a direct clear (CCLR) input and a count-enable (CCKEN) input. For cascading, a  
ripple-carry (RCO) output is provided. Expansion is easily accomplished for two stages by connecting RCO of  
the first stage to CCKEN of the second stage. Cascading for larger count chains can be accomplished by  
connecting RCO of each stage to CCK of the following stage.  
Both the register and the counter have individual positive-edge-triggered clocks. If both clocks are connected  
together, the counter state is always one count ahead of the register. Internal circuitry prevents clocking from  
the clock enable.  
The 74AC11590 is characterized for operation from –40°C to 85°C.  
†
logic symbol  
14  
13  
EN3  
C2  
OE  
RCK  
12  
CTR8  
18  
19  
4
RCO  
G1  
1+  
CT = 0  
CCKEN  
CCK  
(CT = 255) Z4  
17  
CCLR  
20  
1
Q
2D  
3
A
B
C
Q
Q
2
3
Q
Q
Q
Q
Q
D
E
F
8
9
10  
11  
G
H
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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