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74AC11074NSR PDF预览

74AC11074NSR

更新时间: 2024-02-10 03:14:22
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
6页 95K
描述
IC AC SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN, PLASTIC, SOP-14, FF/Latch

74AC11074NSR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.46系列:AC
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:100000000 Hz
最大I(ol):0.024 A湿度敏感等级:1
位数:1功能数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TR
峰值回流温度(摄氏度):260电源:3.3/5 V
最大电源电流(ICC):0.04 mAProp。Delay @ Nom-Sup:8.2 ns
传播延迟(tpd):11.3 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:4.4 mm最小 fmax:125 MHz
Base Number Matches:1

74AC11074NSR 数据手册

 浏览型号74AC11074NSR的Datasheet PDF文件第2页浏览型号74AC11074NSR的Datasheet PDF文件第3页浏览型号74AC11074NSR的Datasheet PDF文件第4页浏览型号74AC11074NSR的Datasheet PDF文件第5页浏览型号74AC11074NSR的Datasheet PDF文件第6页 
74AC11074  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
SCAS499A – DECEMBER 1986 – REVISED APRIL 1996  
D, N, OR PW PACKAGE  
Center-Pin V  
Minimize High-Speed Switching Noise  
and GND Configurations  
CC  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
1PRE  
1Q  
1Q  
GND  
2Q  
1CLK  
1D  
1CLR  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
500-mA Typical Latch-Up Immunity at  
125°C  
V
CC  
Package Options Include Plastic  
Small-Outline (D) and Thin Shrink  
Small-Outline (PW) Packages, and  
Standard Plastic 300-mil DIPs (N)  
2CLR  
2D  
2CLK  
2Q  
2PRE  
8
description  
This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE)  
or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR  
are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the  
outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is  
not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may  
be changed without affecting the levels at the outputs.  
The 74AC11074 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
PRE  
L
CLR  
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
H
L
L
H
X
H
H
L
L
X
H
H
H
H
H
H
L
L
H
H
H
L
X
Q
Q
0
0
This configuration is nonstable; that is, it does not  
persist when PRE or CLR returns to its inactive  
(high) level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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