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5962-9322801MXA PDF预览

5962-9322801MXA

更新时间: 2024-02-09 13:01:10
品牌 Logo 应用领域
德州仪器 - TI 总线控制器微控制器和处理器外围集成电路uCs集成电路uPs集成电路
页数 文件大小 规格书
15页 303K
描述
TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES

5962-9322801MXA 技术参数

生命周期:Active零件包装代码:PGA
包装说明:PGA,针数:69
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.79Is Samacsys:N
JESD-30 代码:S-CPGA-P68端子数量:68
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装形状:SQUARE封装形式:GRID ARRAY
认证状态:Not Qualified筛选级别:MIL-STD-883
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:PIN/PEG端子位置:PERPENDICULAR
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

5962-9322801MXA 数据手册

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SN54ACT8990, SN74ACT8990  
TEST-BUS CONTROLLERS  
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES  
SCAS190E – JUNE 1990 – REVISED JANUARY 1997  
32  
Members of the Texas Instruments  
SCOPE Family of Testability Products  
Execute Instructions for Up to 2 Clock  
Cycles  
Compatible With the IEEE Standard  
1149.1-1990 (JTAG) Test Access Port and  
Boundary-Scan Architecture  
Each Device Includes Four Bidirectional  
Event Pins for Additional Test Capability  
Inputs Are TTL-Voltage Compatible  
Control Operation of Up to Six Parallel  
Target Scan Paths  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
Accommodate Pipeline Delay to Target of  
Up to 31 Clock Cycles  
Packaged in 44-Pin Plastic Leaded Chip  
Carrier (FN), 68-Pin Ceramic Pin Grid Array  
(GB), and 68-Pin Ceramic Quad Flat  
Packages (HV)  
32  
Scan Data Up to 2 Clock Cycles  
description  
The ’ACT8990 test-bus controllers (TBC) are members of the Texas Instruments SCOPE testability  
integrated-circuit family. This family of components supports IEEE Standard 1149.1-1990 (JTAG) boundary  
scan to facilitate testing of complex circuit-board assemblies. The ’ACT8990 differ from other SCOPE  
integrated circuits. Their function is to control the JTAG serial-test bus rather than being target  
boundary-scannable devices.  
TherequiredsignalsoftheJTAGserial-testbustestclock(TCK), testmodeselect(TMS), testdatainput(TDI),  
and test data output (TDO) can be connected from the TBC to a target device without additional logic. This is  
done as a chain of IEEE Standard 1149.1-1990 boundary-scannable components that share the same  
serial-testbus. TheTBCgeneratesTMSandTDIsignalsforitstarget(s), receivesTDOsignalsfromitstarget(s),  
and buffers its test clock input (TCKI) to a test clock output (TCKO) for distribution to its target(s). The TMS, TDI,  
and TDO signals can be connected to a target directly or via a pipeline, with a retiming delay of up to 31 bits.  
Since the TBC can be configured to generate up to six separate TMS signals [TMS (5 0)], it can be used to  
control up to six target scan paths that are connected in parallel (i.e., sharing common TCK, TDI, and TDO  
signals).  
While most operations of the TBC are synchronous to TCKI, a test-off (TOFF) input is provided for output control  
of the target interface, and a test-reset (TRST) input is provided for hardware/software reset of the TBC. In  
addition, four event [EVENT (30)] I/Os are provided for asynchronous communication to target device(s).  
Each event has its own event generation/detection logic, and detected events can be counted by two 16-bit  
counters.  
The TBC operates under the control of a host microprocessor/microcontroller via the 5-bit address bus  
[ADRS (40)] and the 16-bit read/write data bus [DATA (150)]. Read (RD) and write (WR) strobes are  
implemented such that the critical host-interface timing is independent of the TCKI period. Any one of  
24 registers can be addressed for read and/or write operations. In addition to control and status registers, the  
TBC contains two command registers, a read buffer, and a write buffer. Status of the TBC is transmitted to the  
host via ready (RDY) and interrupt (INT) outputs.  
Major commands can be issued by the host to cause the TBC to generate the TMS sequences necessary to  
move the target(s) from any stable test-access-port (TAP) controller state to any other stable TAP state, to  
execute instructions in the Run-Test/Idle TAP state, or to scan instruction or test data through the target(s). A  
32-bit counter can be preset to allow a predetermined number of execution or scan operations.  
Serial data that appears at the selected TDI input (TDI1 or TDI0) is transferred into the read buffer, which can  
be read by the host to obtain up to 16 bits of the serial-data stream. Serial data that is transmitted from the TDO  
output is written by the host to the write buffer.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE and EPIC are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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