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5962-9218301MCA PDF预览

5962-9218301MCA

更新时间: 2024-02-15 04:04:39
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路
页数 文件大小 规格书
20页 1138K
描述
HEX SCHMITT-TRIGGER INVERTER

5962-9218301MCA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:CERPACK-14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.2
Is Samacsys:N系列:ACT
JESD-30 代码:R-GDFP-F14负载电容(CL):50 pF
逻辑集成电路类型:INVERTER最大I(ol):0.024 A
功能数量:6输入次数:1
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装等效代码:FL14,.3
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:12.5 ns传播延迟(tpd):9.5 ns
认证状态:Not Qualified施密特触发器:YES
筛选级别:MIL-STD-883座面最大高度:2.032 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.2865 mm
Base Number Matches:1

5962-9218301MCA 数据手册

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ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢃ ꢈ ꢀꢁꢉ ꢃꢄ ꢅꢆ ꢇꢃ  
ꢊꢋꢌ ꢀꢅꢊ ꢍꢎ ꢆꢆꢏꢆ ꢐꢎꢑ ꢑ ꢋꢐ ꢎ ꢁꢒ ꢋ ꢐꢆ ꢋꢐ  
SCAS557H − DECEMBER 1995 − REVISED NOVEMBER 2004  
D
D
4.5-V to 5.5-V V  
Operation  
D
D
Max t of 11 ns at 5 V  
pd  
Inputs Are TTL-Voltage Compatible  
CC  
Inputs Accept Voltages to 5.5 V  
SN54ACT14 . . . J OR W PACKAGE  
SN74ACT14 . . . D, DB, N, NS. OR PW PACKAGE  
(TOP VIEW)  
SN54ACT14 . . . FK PACKAGE  
(TOP VIEW)  
1A  
1Y  
V
CC  
1
2
3
4
5
6
7
14  
3
2
1 20 19  
18  
13 6A  
12 6Y  
11 5A  
6Y  
NC  
5A  
NC  
5Y  
2A  
NC  
2Y  
4
5
6
7
8
2A  
17  
16  
15  
14  
2Y  
10  
9
3A  
5Y  
4A  
4Y  
NC  
3A  
3Y  
8
GND  
9 10 11 12 13  
NC − No internal connection  
description/ordering information  
These Schmitt-trigger devices contain six independent inverters. They perform the Boolean function Y = A.  
Because of the Schmitt action, they have different input threshold levels for positive-going (V ) and for  
T+  
negative-going (V ) signals.  
T−  
These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give  
clean, jitter-free output signals. They also have a greater noise margin than conventional inverters.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube  
SN74ACT14N  
SN74ACT14N  
Tube  
SN74ACT14D  
ACT14  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74ACT14DR  
SN74ACT14NSR  
SN74ACT14DBR  
SN74ACT14PW  
SN74ACT14PWR  
SNJ54ACT14J  
SNJ54ACT14W  
SNJ54ACT14FK  
SOP − NS  
ACT14  
AD14  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
AD14  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54ACT14J  
SNJ54ACT14W  
SNJ54ACT14FK  
Tube  
−55°C to 125°C  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each inverter)  
INPUT  
A
OUTPUT  
Y
H
L
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2004, Texas Instruments Incorporated  
ꢔ ꢘ ꢣ ꢛ ꢚꢦ ꢡꢠ ꢞꢟ ꢠꢚ ꢜꢣ ꢥꢗ ꢝꢘ ꢞ ꢞꢚ ꢍꢎ ꢭꢏ ꢓꢐ ꢮ ꢏꢯꢰꢂ ꢯꢂꢈ ꢝꢥꢥ ꢣꢝ ꢛ ꢝ ꢜꢢ ꢞꢢꢛ ꢟ ꢝ ꢛ ꢢ ꢞꢢ ꢟꢞꢢ ꢦ  
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ  
ꢡ ꢘꢥ ꢢꢟꢟ ꢚ ꢞꢨꢢ ꢛ ꢪꢗ ꢟꢢ ꢘ ꢚꢞꢢ ꢦꢧ ꢔ ꢘ ꢝꢥ ꢥ ꢚ ꢞꢨꢢ ꢛ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢟ ꢈ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢗꢚ ꢘ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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