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5962-8985201EA PDF预览

5962-8985201EA

更新时间: 2024-02-24 01:02:27
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
14页 278K
描述
High-Speed CMOS Logic 8-Bit Addressable Latch

5962-8985201EA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:CERAMIC, DIP-16针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.25Is Samacsys:N
其他特性:1:8 DMUX FOLLOWED BY LATCH系列:HCT
JESD-30 代码:R-GDIP-T16长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:D LATCH
最大I(ol):0.004 A位数:1
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):57 ns认证状态:Qualified
筛选级别:MIL-STD-883座面最大高度:5.08 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:LOW LEVEL宽度:7.62 mm
Base Number Matches:1

5962-8985201EA 数据手册

 浏览型号5962-8985201EA的Datasheet PDF文件第2页浏览型号5962-8985201EA的Datasheet PDF文件第3页浏览型号5962-8985201EA的Datasheet PDF文件第4页浏览型号5962-8985201EA的Datasheet PDF文件第5页浏览型号5962-8985201EA的Datasheet PDF文件第6页浏览型号5962-8985201EA的Datasheet PDF文件第7页 
CD54HC259, CD74HC259,  
CD54HCT259, CD74HCT259  
Data sheet acquired from Harris Semiconductor  
SCHS173C  
High-Speed CMOS Logic  
8-Bit Addressable Latch  
November 1997 - Revised October 2003  
Features  
Description  
• Buffered Inputs and Outputs  
• Four Operating Modes  
• Typical Propagation Delay of 15ns at V  
The ’HC259 and ’HCT259 Addressable Latch features the  
low-power consumption associated with CMOS circuitry and  
has speeds comparable to low-power Schottky.  
[ /Title  
(CD74  
HC259  
,
CD74  
HCT25  
9)  
= 5V,  
CC  
This latches three active modes and one reset mode. When  
both the Latch Enable (LE) and Master Reset (MR) inputs are  
low (8-line Demultiplexer mode) the output of the addressed  
latch follows the Data input and all other outputs are forced  
low. When both MR and LE are high (Memory Mode), all  
outputs are isolated from the Data input, i.e., all latches hold  
o
C = 15pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C the last data presented before the LE transition from low to  
high. A condition of LE low and MR high (Addressable Latch  
mode) allows the addressed latch’s output to follow the data  
input; all other latches are unaffected. The Reset mode (all  
outputs low) results when LE is high and MR is low.  
/Sub-  
ject  
• Balanced Propagation Delay and Transition Times  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
(High  
Speed  
CMOS  
Logic  
8-Bit  
Addres  
sable  
Latch)  
• HC Types  
Ordering Information  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
CC  
TEMP. RANGE  
o
IL  
IH  
PART NUMBER  
CD54HC259F3A  
CD54HCT259F3A  
CD74HC259E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
at V  
= 5V  
CC  
• HCT Types  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
CD74HC259M  
CD74HC259MT  
CD74HC259M96  
CD74HCT259E  
CD74HCT259M  
CD74HCT259MT  
CD74HCT259M96  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel  
of 250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

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