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5962-8852001VDA PDF预览

5962-8852001VDA

更新时间: 2024-01-15 07:09:56
品牌 Logo 应用领域
德州仪器 - TI 触发器逻辑集成电路
页数 文件大小 规格书
17页 543K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

5962-8852001VDA 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.02系列:AC
JESD-30 代码:R-CDFP-F14逻辑集成电路类型:D FLIP-FLOP
位数:1功能数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
传播延迟(tpd):17.5 ns认证状态:Not Qualified
筛选级别:MIL-STD-883最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子位置:DUAL触发器类型:POSITIVE EDGE
最小 fmax:140 MHzBase Number Matches:1

5962-8852001VDA 数据手册

 浏览型号5962-8852001VDA的Datasheet PDF文件第2页浏览型号5962-8852001VDA的Datasheet PDF文件第3页浏览型号5962-8852001VDA的Datasheet PDF文件第4页浏览型号5962-8852001VDA的Datasheet PDF文件第5页浏览型号5962-8852001VDA的Datasheet PDF文件第6页浏览型号5962-8852001VDA的Datasheet PDF文件第7页 
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ꢈꢉꢄ ꢊ ꢋꢌ ꢀꢍ ꢎ ꢍꢏꢐ ꢑꢐꢈꢒ ꢐꢑꢎ ꢓꢍ ꢒ ꢒꢐ ꢓꢐꢈ ꢈꢑꢎ ꢔꢋ ꢐ ꢕ ꢊꢍ ꢋ ꢑꢕ ꢊꢌ ꢋꢀ  
ꢖ ꢍꢎ ꢗ ꢅꢊ ꢐꢄꢓ ꢄꢁꢈ ꢋ ꢓꢐ ꢀ ꢐꢎ  
SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003  
SN54AC74 . . . J OR W PACKAGE  
SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
2-V to 6-V V  
Operation  
CC  
Inputs Accept Voltages to 6 V  
Max t of 10 ns at 5 V  
pd  
1CLR  
1D  
V
CC  
13 2CLR  
12 2D  
1
2
3
4
5
6
7
14  
description/ordering information  
1CLK  
1PRE  
1Q  
The ’AC74 devices are dual positive-edge-  
triggered D-type flip-flops.  
11 2CLK  
10  
9
2PRE  
2Q  
A low level at the preset (PRE) or clear (CLR) input  
sets or resets the outputs, regardless of the levels  
of the other inputs. When PRE and CLR are  
inactive (high), data at the data (D) input meeting  
the setup-time requirements is transferred to the  
outputs on the positive-going edge of the clock  
pulse. Clock triggering occurs at a voltage level  
and is not directly related to the rise time of the  
clock pulse. Following the hold-time interval, data  
at D can be changed without affecting the levels  
at the outputs.  
1Q  
8
GND  
2Q  
SN54AC74 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
2D  
1CLK  
NC  
4
5
6
7
8
NC  
17  
16  
15  
14  
2CLK  
NC  
1PRE  
NC  
2PRE  
1Q  
9 10 11 12 13  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube  
SN74AC74N  
SN74AC74N  
Tube  
SN74AC74D  
AC74  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74AC74DR  
SN74AC74NSR  
SN74AC74DBR  
SN74AC74PW  
SN74AC74PWR  
SNJ54AC74J  
SNJ54AC74W  
SNJ54AC74FK  
SOP − NS  
AC74  
AC74  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
AC74  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54AC74J  
Tube  
SNJ54AC74W  
SNJ54AC74FK  
−55°C to 125°C  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢌ ꢙ ꢤ ꢜ ꢛꢧ ꢢꢡ ꢟꢠ ꢡꢛ ꢝꢤ ꢦꢘ ꢞꢙ ꢟ ꢟꢛ ꢮꢍ ꢊꢑ ꢋꢓ ꢕ ꢑꢯꢰꢂ ꢯꢂꢇ ꢞꢦꢦ ꢤꢞ ꢜ ꢞ ꢝꢣ ꢟꢣꢜ ꢠ ꢞ ꢜ ꢣ ꢟꢣ ꢠꢟꢣ ꢧ  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢢ ꢙꢦ ꢣꢠꢠ ꢛ ꢟꢩꢣ ꢜ ꢫꢘ ꢠꢣ ꢙ ꢛꢟꢣ ꢧꢨ ꢌ ꢙ ꢞꢦ ꢦ ꢛ ꢟꢩꢣ ꢜ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢠ ꢇ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛ ꢙ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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