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5962-8752501SCA PDF预览

5962-8752501SCA

更新时间: 2024-01-04 20:08:15
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
16页 529K
描述
ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14

5962-8752501SCA 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP, FL14,.3针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.1系列:ACT
JESD-30 代码:R-GDFP-F14JESD-609代码:e0
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:85000000 Hz最大I(ol):0.024 A
位数:1功能数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL14,.3封装形状:RECTANGULAR
封装形式:FLATPACK电源:5 V
传播延迟(tpd):14 ns认证状态:Not Qualified
筛选级别:MIL-PRF-38535座面最大高度:2.032 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:TIN LEAD
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:6.2865 mm最小 fmax:95 MHz
Base Number Matches:1

5962-8752501SCA 数据手册

 浏览型号5962-8752501SCA的Datasheet PDF文件第2页浏览型号5962-8752501SCA的Datasheet PDF文件第3页浏览型号5962-8752501SCA的Datasheet PDF文件第4页浏览型号5962-8752501SCA的Datasheet PDF文件第5页浏览型号5962-8752501SCA的Datasheet PDF文件第6页浏览型号5962-8752501SCA的Datasheet PDF文件第7页 
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ꢖ ꢎꢆ ꢗ ꢅꢋ ꢐꢄꢓ ꢄꢁꢉ ꢌ ꢓꢐ ꢀ ꢐꢆ  
SCAS520H − AUGUST 1995 − REVISED OCTOBER 2003  
D
D
4.5-V to 5.5-V V  
Operation  
D
Max t of 10.5 ns at 5 V  
pd  
Inputs Are TTL-Voltage Compatible  
CC  
Inputs Accept Voltages to 5.5 V  
D
SN54ACT74 . . . J OR W PACKAGE  
SN74ACT74 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
SN54ACT74 . . . FK PACKAGE  
(TOP VIEW)  
1CLR  
1D  
V
CC  
13 2CLR  
12 2D  
1
2
3
4
5
6
7
14  
3
2
1
20 19  
18  
2D  
1CLK  
NC  
1CLK  
1PRE  
1Q  
4
5
6
7
8
NC  
17  
16  
15  
14  
11  
10  
9
2CLK  
2PRE  
2Q  
2CLK  
NC  
1PRE  
NC  
1Q  
2PRE  
1Q  
8
GND  
2Q  
9 10 11 12 13  
NC − No internal connection  
description/ordering information  
The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops.  
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,  
data at D can be changed without affecting the levels at the outputs.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube  
SN74ACT74N  
SN74ACT74N  
Tube  
SN74ACT74D  
ACT74  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74ACT74DR  
SN74ACT74NSR  
SN74ACT74DBR  
SN74ACT74PW  
SN74ACT74PWR  
SNJ54ACT74J  
SNJ54ACT74W  
SNJ54ACT74FK  
SOP − NS  
ACT74  
AD74  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
AD74  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54ACT74J  
SNJ54ACT74W  
SNJ54ACT74FK  
Tube  
−55°C to 125°C  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
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ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢢ ꢙꢦ ꢣꢠꢠ ꢛ ꢟꢩꢣ ꢜ ꢫꢘ ꢠꢣ ꢙ ꢛꢟꢣ ꢧꢨ ꢍ ꢙ ꢞꢦ ꢦ ꢛ ꢟꢩꢣ ꢜ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢠ ꢈ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛ ꢙ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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