CD54HC74, CD74HC74,
CD54HCT74, CD74HCT74
Data sheet acquired from Harris Semiconductor
SCHS124D
Dual D Flip-Flop with Set and Reset
Positive-Edge Trigger
January 1998 - Revised September 2003
Features
Description
• Hysteresis on Clock Inputs for Improved Noise The ’HC74 and ’HCT74 utilize silicon gate CMOS technology
Immunity and Increased Input Rise and Fall Times
• Asynchronous Set and Reset
• Complementary Outputs
to achieve operating speeds equivalent to LSTTL parts.
They exhibit the low power consumption of standard CMOS
integrated circuits, together with the ability to drive 10 LSTTL
loads.
[ /Title
(CD54H
C74,
CD74H
C74,
This flip-flop has independent DATA, SET, RESET and
CLOCK inputs and Q and Q outputs. The logic level present
at the data input is transferred to the output during the
positive-going transition of the clock pulse. SET and RESET
are independent of the clock and are accomplished by a low
level at the appropriate input.
• Buffered Inputs
• Typical f
MAX
= 50MHz at V = 5V, C = 15pF,
CC L
o
CD74H
CT74)
/Subject
(Dual D
Flip-
T = 25 C
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The HCT logic family is functionally as well as pin compatible
with the standard LS logic family.
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Flop
with Set
Ordering Information
TEMP. RANGE
• Significant Power Reduction Compared to LSTTL
Logic ICs
o
PART NUMBER
CD54HC74F3A
( C)
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• HC Types
CD54HCT74F3A
CD74HC74E
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
CC
IL
IH
at V
= 5V
CC
CD74HC74M
• HCT Types
CD74HC74MT
CD74HC74M96
CD74HCT74E
CD74HCT74M
CD74HCT74MT
CD74HCT74M96
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1