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5962-0720401VXC PDF预览

5962-0720401VXC

更新时间: 2024-01-14 04:46:19
品牌 Logo 应用领域
德州仪器 - TI 转换器数模转换器
页数 文件大小 规格书
23页 584K
描述
CLASS V, 14-BIT, 400-MSPS DIGITAL-TO-ANALOG CONVERTER

5962-0720401VXC 技术参数

生命周期:Active零件包装代码:QFP
包装说明:QFF, TPAK52,1.6SQ,25针数:52
Reach Compliance Code:not_compliantECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:5.38
Is Samacsys:N最大模拟输出电压:3.9 V
最小模拟输出电压:2.15 V转换器类型:D/A CONVERTER
输入位码:COMPLEMENTARY BINARY输入格式:PARALLEL, WORD
JESD-30 代码:S-CQFP-F52长度:13.97 mm
最大线性误差 (EL):0.0281%位数:14
功能数量:1端子数量:52
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QFF
封装等效代码:TPAK52,1.6SQ,25封装形状:SQUARE
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Qualified
采样速率:400 MHz筛选级别:38535V;38534K;883S
座面最大高度:3.42 mm标称安定时间 (tstl):0.012 µs
子类别:Other Converters最大压摆率:148 mA
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:FLAT端子节距:0.64 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
总剂量:100k Rad(Si) V宽度:13.97 mm
Base Number Matches:1

5962-0720401VXC 数据手册

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DAC5675A-SP  
www.ti.com ..................................................................................................................................................... SGLS387D JULY 2007REVISED OCTOBER 2009  
CLASS V, 14-BIT, 400-MSPS DIGITAL-TO-ANALOG CONVERTER  
Check for Samples: DAC5675A-SP  
1
FEATURES  
QML-V Qualified, SMD 5962-07204  
400-MSPS Update Rate  
Military Temperature Range (–55°C to 125°C)  
LVDS-Compatible Input Interface  
APPLICATIONS  
Spurious-Free Dynamic Range (SFDR) to  
Nyquist  
Cellular Base Transceiver Station Transmit  
Channel:  
69 dBc at 70 MHz IF, 400 MSPS  
CDMA: WCDMA, CDMA2000, IS-95  
TDMA: GSM, IS-136, EDGE/GPRS  
Supports Single-Carrier and Multicarrier  
Applications  
W-CDMA Adjacent Channel Power Ratio  
(ACPR)  
73 dBc at 30.72 MHz IF, 122.88 MSPS  
71 dBc at 61.44 MHz IF, 245.76 MSPS  
Test and Measurement: Arbitrary Waveform  
Generation  
Differential Scalable Current Outputs:  
2 mA to 20 mA  
On-Chip 1.2-V Reference  
Single 3.3-V Supply Operation  
Power Dissipation: 660 mW at  
fCLK = 400 MSPS, fOUT = 20 MHz  
High-Performance 52-Pin Ceramic Quad Flat  
Pack (HFG)  
DESCRIPTION/ORDERING INFORMATION  
The DAC5675A is a 14-bit resolution high-speed digital-to-analog converter (DAC). The DAC5675A is designed  
for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct  
digital synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A has  
excellent spurious-free dynamic range (SFDR) at high intermediate frequencies, which makes it well suited for  
multicarrier transmission in TDMA and CDMA based cellular base transceiver stations (BTSs).  
The DAC5675A operates from a single supply voltage of 3.3 V. Power dissipation is 660 mW at  
fCLK = 400 MSPS, fOUT = 70 MHz. The DAC5675A provides a nominal full-scale differential current output of  
20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the  
load with no additional external output buffer required. The output is referred to the analog supply voltage AVDD  
.
The DAC5675A includes a low-voltage differential signaling (LVDS) interface for high-speed digital data input.  
LVDS features a low differential voltage swing with a low constant power consumption across frequency,  
allowing for high-speed data transmission with low noise levels; that is, with low electromagnetic interference  
(EMI). LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for  
high-speed interfacing between the DAC5675A and high-speed low-voltage CMOS ASICs or FPGAs. The  
DAC5675A current-source-array architecture supports update rates of up to 400 MSPS. On-chip edge-triggered  
input latches provide for minimum setup and hold times, thereby relaxing interface timing.  
The DAC5675A is specifically designed for  
a differential transformer-coupled output with a 50-  
doubly-terminated load. With the 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an  
output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm) is supported. The last configuration is  
preferred for optimum performance at high output frequencies and update rates. The outputs are terminated to  
AVDD and have voltage compliance ranges from AVDD – 1 to AVDD + 0.3 V.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2007–2009, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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